Jason A. Cheatham

According to our database1, Jason A. Cheatham authored at least 5 papers between 2000 and 2006.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2006
A survey of fault tolerant methodologies for FPGAs.
ACM Trans. Design Autom. Electr. Syst., 2006

2003
An FFT Approximation Technique Suitable for On-Chip Generation and Analysis of Sinusoidal Signals.
Proceedings of the 18th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2003), 2003

A Monolithic Spectral BIST Technique for Control or Test of Analog or Mixed-Signal Circuits.
Proceedings of the 18th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2003), 2003

2001
On-Line Incremental Routing for Interconnect Fault Tolerance in FPGAs Minus the Router .
Proceedings of the 16th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2001), 2001

2000
Performance Penalty for Fault Tolerance in Roving STARs.
Proceedings of the Field-Programmable Logic and Applications, 2000


  Loading...