Jaroslav Borecký

According to our database1, Jaroslav Borecký authored at least 11 papers between 2009 and 2024.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

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Bibliography

2024
Quantized Neural Network with Linearly Approximated Functions on Zynq FPGA.
Proceedings of the 13th Mediterranean Conference on Embedded Computing, 2024

2023
Evaluation of the Medium-sized Neural Network using Approximative Computations on Zynq FPGA.
Proceedings of the 12th Mediterranean Conference on Embedded Computing, 2023

2020
Evaluation of the SEU Faults Coverage of a Simple Fault Model for Application-Oriented FPGA Testing.
Proceedings of the 23rd Euromicro Conference on Digital System Design, 2020

2017
Parity driven reconfigurable duplex system.
Microprocess. Microsystems, 2017

2016
Enhanced Duplication Method with TMR-Like Masking Abilities.
Proceedings of the 2016 Euromicro Conference on Digital System Design, 2016

Parity Waterfall method.
Proceedings of the 2016 IEEE 19th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS), 2016

2014
Fault Tolerant Duplex System with High Availability for Practical Applications.
Proceedings of the 17th Euromicro Conference on Digital System Design, 2014

2012
Miscellaneous Types of Partial Duplication Modifications for Availability Improvements.
Proceedings of the 15th Euromicro Conference on Digital System Design, 2012

2011
Fault Models Usability Study for On-line Tested FPGA.
Proceedings of the 14th Euromicro Conference on Digital System Design, 2011

2010
Faults Coverage Improvement Based on Fault Simulation and Partial Duplication.
Proceedings of the 13th Euromicro Conference on Digital System Design, 2010

2009
Reliable Railway Station System Based on Regular Structure Implemented in FPGA.
Proceedings of the 12th Euromicro Conference on Digital System Design, 2009


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