Jarom Peña

According to our database, Jarom Peña authored at least 3 papers between 2007 and 2012.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2012

Voltage droop reduction using throttling controlled by timing margin feedback.

Michael S. Floyd, Alan J. Drake, Robert W. Berry, Harold Chase, Richard L. Willaman, Jarom Peña

Proceedings of the Symposium on VLSI Circuits, 2012

2008

On-chip jitter and oscilloscope circuits using an asynchronous sample clock.

Jeremy D. Schaub, Fadi H. Gebara, Tuyet Nguyen, Ivan Vo, Jarom Peña, Dhruva J. Acharyya

Proceedings of the ESSCIRC 2008, 2008

2007

A 1V 18GHz Clock Generator in a 65nm PD-SOI Technology.

Fadi H. Gebara, Jeremy D. Schaub, Tuyet Nguyen, Jarom Peña, Ivan Vo, David Boerstler, Kevin J. Nowka

Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007