Jarkko Niittylahti

According to our database1, Jarkko Niittylahti authored at least 31 papers between 1993 and 2011.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Bibliography

2011
Corento - SIMD Parallelism from Portable High-Level Code.
Proceedings of the Applications, Tools and Techniques on the Road to Exascale Computing, Proceedings of the conference ParCo 2011, 31 August, 2011

2005
On Design of Parallel Memory Access Schemes for Video Coding.
J. VLSI Signal Process., 2005

2004
Scalable Parallel Memory Architectures for Video Coding.
J. VLSI Signal Process., 2004

Byte and modulo addressable parallel memory architecture for video coding.
IEEE Trans. Circuits Syst. Video Technol., 2004

DRAM performance as a function of its structure and memory stream locality.
Microprocess. Microsystems, 2004

Scalar Metric for Temporal Locality and Estimation of Cache Performance.
Proceedings of the 2004 Design, 2004

2003
An Approach to Adaptive Enhancement of Diagnostic X-Ray Images.
EURASIP J. Adv. Signal Process., 2003

Wireless technologies for data acquisition systems.
Proceedings of the 1st Intenational Symposium on Information and Communication Technologies, 2003

A low-power, memoryless direct digital frequency synthesizer architecture.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

Quadrature direct digital frequency synthesizer using an angle rotation algorithm.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

TraceAnalyzer - an open framework for memory stream analysis.
Proceedings of the 2003 10th IEEE International Conference on Electronics, 2003

2002
High-performance implementation of wavelet algorithms on a standard PC.
Microprocess. Microsystems, 2002

DRAM simulator for design and analysis of digital systems.
Microprocess. Microsystems, 2002

Configurable parallel memory architecture for multimedia computers.
J. Syst. Archit., 2002

Medical isolation of universal serial bus data signals.
Proceedings of the 2002 9th IEEE International Conference on Electronics, 2002

Direct digital frequency synthesizers of high spectral purity based on quadratic approximation.
Proceedings of the 2002 9th IEEE International Conference on Electronics, 2002

A comparison of precharge policies with modern DRAM architectures.
Proceedings of the 2002 9th IEEE International Conference on Electronics, 2002

Adaptive FIR filter architectures for run-time reconfigurable FPGAs.
Proceedings of the 2002 IEEE International Conference on Field-Programmable Technology, 2002

System-Level Modelling and Implementation Technique for Run-Time Reconfigurable Systems.
Proceedings of the 10th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2002), 2002

2001
A hardware efficient direct digital frequency synthesizer.
Proceedings of the 2001 8th IEEE International Conference on Electronics, 2001

2000
Parallel, memory access schemes for H.263 encoder.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000

A Hybrid Prototyping Platform for Dynamically Reconfigurable Designs.
Proceedings of the Field-Programmable Logic and Applications, 2000

Evaluation of RSSI-based human tracking.
Proceedings of the 10th European Signal Processing Conference, 2000

Complex digital oscillator with absolute periodicity.
Proceedings of the 10th European Signal Processing Conference, 2000

Verifying external data memory interface for H.263 video DSP with memory simulator.
Proceedings of the 10th European Signal Processing Conference, 2000

1999
Area-optimized FPGA implementation of a digital FM modulator.
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

Numerical sine and cosine synthesis using a complex multiplier.
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

Parallel Memories in Video Encoding.
Proceedings of the Data Compression Conference, 1999

1998
Fast Prototyping Using System Emulators.
Proceedings of the Field-Programmable Logic and Applications, 1998

1996
Hardware Prototypes of a Boolean Neural Network and the Simulated Annealing Optimization Method.
Int. J. Neural Syst., 1996

1993
Dynamically Configurable Combinatory Logic Array as Boolean Neural Network.
Proceedings of the Fifth International Conference on Tools with Artificial Intelligence, 1993


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