Jared Zerbe

According to our database, Jared Zerbe authored at least 22 papers between 1994 and 2015.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2015

A 40 Gb/s Serial Link Transceiver in 28 nm CMOS Technology.

Reza Navid, E-Hung Chen, Masum Hossain, Brian S. Leibowitz, Jihong Ren, Chuen-Huei Adam Chou, Barry Daly, Marko Aleksic, Bruce Su, Simon Li, Makarand Shirasgaonkar, Fred Heaton, Jared Zerbe, John C. Eble

IEEE J. Solid State Circuits, 2015

2014

A Fast-Lock, Jitter Filtering All-Digital DLL Based Burst-Mode Memory Interface.

Masum Hossain, Farrukh Aquil, Pak Shing Chau, Brian Tsang, Phuong Le, Jason Wei, Teva Stone, Barry Daly, Chanh Tran, John C. Eble, Kurt Knorpp, Jared Zerbe

IEEE J. Solid State Circuits, 2014

A 4×40 Gb/s quad-lane CDR with shared frequency tracking and data dependent jitter filtering.

Masum Hossain, E-Hung Chen, Reza Navid, Brian S. Leibowitz, Chuen-Huei Adam Chou, Simon Li, Myeong-Jae Park, Jihong Ren, Barry Daly, Bruce Su, Makarand Shirasgaonkar, Fred Heaton, Jared Zerbe, John C. Eble

Proceedings of the Symposium on VLSI Circuits, 2014

2012

A 27-Gb/s, 0.41-mW/Gb/s 1-tap predictive decision feedback equalizer in 40-nm low-power CMOS.

Kambiz Kaviani, Masum Hossain, Meisam Honarvar Nazari, Fred Heaton, Jihong Ren, Jared Zerbe

Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, 2012

A 6.4/3.2/1.6 Gb/s low power interface with all digital clock multiplier for on-the-fly rate switching.

Masum Hossain, Kambiz Kaviani, Barry Daly, Makarand Shirasgaonkar, Wayne D. Dettloff, Teva Stone, Kashinath Prabhu, Brian Tsang, John C. Eble, Jared Zerbe

Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, 2012

A 2.3-4GHz injection-locked clock multiplier with 55.7% lock range and 10-ns power-on.

Dustin Dunwell, Anthony Chan Carusone, Jared Zerbe, Brian S. Leibowitz, Barry Daly, John C. Eble

Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, 2012

2011

Equalizer Design and Performance Trade-Offs in ADC-Based Serial Links.

Jaeha Kim, E-Hung Chen, Jihong Ren, Brian S. Leibowitz, Patrick Satarzadeh, Jared Zerbe, Chih-Kong Ken Yang

IEEE Trans. Circuits Syst. I Regul. Pap., 2011

A 5 Gb/s Link With Matched Source Synchronous and Common-Mode Clocking Techniques.

Jared Zerbe, Barry Daly, Lei Luo, Bill Stonecypher, Wayne D. Dettloff, John C. Eble, Teva Stone, Jihong Ren, Brian S. Leibowitz, Michael Bucher, Patrick Satarzadeh, Qi Lin, Yue Lu, Ravi T. Kollipara

IEEE J. Solid State Circuits, 2011

Power-efficient I/O design considerations for high-bandwidth applications.

John C. Eble, Scott Best, Brian S. Leibowitz, Lei Luo, Robert Palmer, John M. Wilson, Jared Zerbe, Amir Amirkhany, Nhat Nguyen

Proceedings of the 2011 IEEE Custom Integrated Circuits Conference, 2011

2010

Equalizer design and performance trade-offs in ADC-based serial links.

Jaeha Kim, Jihong Ren, Brian S. Leibowitz, Patrick Satarzadeh, Ali-Azam Abbasfar, Jared Zerbe

Proceedings of the IEEE Custom Integrated Circuits Conference, 2010

2009

A 16 Gb/s/Link, 64 GB/s Bidirectional Asymmetric Memory Interface.

Haechang Lee, Kun-Yung Ken Chang, Jung-Hoon Chun, Ting Wu, Yohan Frans, Brian S. Leibowitz, Nhat Nguyen, T. J. Chin, Kambiz Kaviani, Jie Shen, Xudong Shi, Wendemagegnehu T. Beyene, Simon Li, Reza Navid, Marko Aleksic, Fred S. Lee, Fredy Quan, Jared Zerbe, Rich Perego, Fariborz Assaderaghi

IEEE J. Solid State Circuits, 2009

2008

Near-Optimal Equalizer and Timing Adaptation for I/O Links Using a BER-Based Metric.

E-Hung Chen, Jihong Ren, Brian S. Leibowitz, Hae-Chang Lee, Qi Lin, Kyung Suk Oh, Frank Lambrecht, Vladimir Stojanovic, Jared Zerbe, Chih-Kong Ken Yang

IEEE J. Solid State Circuits, 2008

2007

A 7.5Gb/s 10-Tap DFE Receiver with First Tap Partial Response, Spectrally Gated Adaptation, and 2nd-Order Data-Filtered CDR.

Brian S. Leibowitz, Jade Kizer, Haechang Lee, Fred Chen, Andrew Ho, Metha Jeeradit, Akash Bansal, Trey Greer, Simon Li, Ramin Farjad-Rad, William F. Stonecypher, Yohan Frans, Barry Daly, Fred Heaton, Bruno W. Garlepp, Carl W. Werner, Nhat Nguyen, Vladimir Stojanovic, Jared Zerbe

Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007

2006

Improving CDR Performance via Estimation.

Haechang Lee, Akash Bansal, Yohan Frans, Jared Zerbe, Stefanos Sidiropoulos, Mark Horowitz

Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006

2005

Autonomous dual-mode (PAM2/4) serial link transceiver with adaptive equalization and data recovery.

Vladimir Stojanovic, Andrew Ho, Bruno W. Garlepp, Fred Chen, Jason Wei, Grace Tsang, Elad Alon, Ravi T. Kollipara, Carl W. Werner, Jared L. Zerbe, Mark A. Horowitz

IEEE J. Solid State Circuits, 2005

Modeling, simulation, and design of a multi-mode 2-10 Gb/sec fully adaptive serial link system.

Carl W. Werner, C. Hoyer, Andrew Ho, Metha Jeeradit, Fred Chen, Bruno W. Garlepp, Bill Stonecypher, Simon Li, Akash Bansal, Amita Agarwal, Elad Alon, Vladimir Stojanovic, Jared Zerbe

Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005

2003

Equalization and clock recovery for a 2.5-10-Gb/s 2-PAM/4-PAM backplane transceiver cell.

Jared L. Zerbe, Carl W. Werner, Vladimir Stojanovic, Fred Chen, Jason Wei, Grace Tsang, Dennis Kim, William F. Stonecypher, Andrew Ho, Timothy P. Thrush, Ravi T. Kollipara, Mark A. Horowitz, Kevin S. Donnelly

IEEE J. Solid State Circuits, 2003

Transition-limiting codes for 4-PAM signaling in high speed serial links.

Anthony G. Bessios, William F. Stonecypher, Amita Agarwal, Jared Zerbe

Proceedings of the Global Telecommunications Conference, 2003

2001

1.6 Gb/s/pin 4-PAM signaling and circuits for a multidrop bus.

Jared L. Zerbe, Pak Shing Chau, Carl W. Werner, Timothy P. Thrush, H. J. Liaw, Bruno W. Garlepp, Kevin S. Donnelly

IEEE J. Solid State Circuits, 2001

1999

A portable digital DLL for high-speed CMOS interface circuits.

Bruno W. Garlepp, Kevin S. Donnelly, Jun Kim, Pak Shing Chau, Jared L. Zerbe, Charlie Huang, Chanh Tran, Clemenz L. Portmann, Donald Stark, Yiu-Fai Chan, Thomas H. Lee, Mark A. Horowitz

IEEE J. Solid State Circuits, 1999

1998

A process-independent, 800-MB/s, DRAM byte-wide interface featuring command interleaving and concurrent memory operation.

Matthew M. Griffin, Jared Zerbe, Grace Tsang, Michael Ching, Clemenz L. Portmann

IEEE J. Solid State Circuits, 1998

1994

A 2.5 V CMOS delay-locked loop for 18 Mbit, 500 megabyte/s DRAM.

Thomas H. Lee, Kevin S. Donnelly, John T. C. Ho, Jared Zerbe, Mark Johnson, Tom Ishikawa

IEEE J. Solid State Circuits, December, 1994