Janier Arias-Garcia
Orcid: 0000-0001-5203-3048
According to our database1,
Janier Arias-Garcia
authored at least 16 papers
between 2011 and 2024.
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Bibliography
2024
Improved Design for Hardware Implementation of Graph-Based Large Margin Classifiers for Embedded Edge Computing.
IEEE Trans. Neural Networks Learn. Syst., January, 2024
2023
IEEE Trans. Instrum. Meas., 2023
Proceedings of the 36th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems Design, 2023
2021
Enhancing Performance of Gabriel Graph-Based Classifiers by a Hardware Co-Processor for Embedded System Applications.
IEEE Trans. Ind. Informatics, 2021
Comput. Electr. Eng., 2021
A New Automated Energy Meter Fraud Detection System Based on Artificial Intelligence.
Proceedings of the XI Brazilian Symposium on Computing Systems Engineering, 2021
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021
2019
Simplification of the digital representation of the tent map through biased fixed point.
CoRR, 2019
2018
2016
Efficient hardware implementation of the Richardson-Lucy Algorithm for restoring motion-blurred image on reconfigurable digital system.
Proceedings of the 29th Symposium on Integrated Circuits and Systems Design, 2016
2014
Implementação em hardware reconfigurável de operadores matriciais para solução numérica de sistemas lineares.
PhD thesis, 2014
Verification of Hardware Implementations through Correctness of their Recursive Definitions in PVS.
Proceedings of the 27th Symposium on Integrated Circuits and Systems Design, 2014
2012
Int. J. Reconfigurable Comput., 2012
Hardware implementation of GMDH-type artificial neural networks and its use to predict approximate three-dimensional structures of proteins.
Proceedings of the 7th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC), 2012
2011
Proceedings of the 24th Symposium on Integrated Circuits and Systems Design, 2011