Jani K. Jarvenhaara

According to our database1, Jani K. Jarvenhaara authored at least 11 papers between 2013 and 2020.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2020
A Two-Stage LNA Design for 28GHz Band Of 5G on 45nm CMOS.
Proceedings of the 63rd IEEE International Midwest Symposium on Circuits and Systems, 2020

2016
A variable battery supply dc-dc buck converter designed for 45 nm-CMOS technology.
Proceedings of the 2016 IEEE Canadian Conference on Electrical and Computer Engineering, 2016

On moderate inversion/saturation regions as approximations to "reconciliation" model.
Proceedings of the 2016 IEEE Canadian Conference on Electrical and Computer Engineering, 2016

2015
High speed DC-DC dead time architecture.
IEICE Electron. Express, 2015

Cascoded power stage with automatic dead time generation.
Proceedings of the IEEE 58th International Midwest Symposium on Circuits and Systems, 2015

An asymmetric VHF self-oscillating DC-DC converter with integrated transformer.
Proceedings of the IEEE 58th International Midwest Symposium on Circuits and Systems, 2015

Determining potentially unstable operating points using time-varying root-locus.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

2014
A 3.6-to-1.8-V Cascode Buck Converter With a Stacked LC Filter in 65-nm CMOS.
IEEE Trans. Circuits Syst. II Express Briefs, 2014

On design of low-voltage CMOS current amplifiers.
Proceedings of the IEEE 57th International Midwest Symposium on Circuits and Systems, 2014

2013
Source follower: A misunderstood humble circuit.
Proceedings of the IEEE 56th International Midwest Symposium on Circuits and Systems, 2013

Push-pull RC-oscillator/multivibrator.
Proceedings of the IEEE 56th International Midwest Symposium on Circuits and Systems, 2013


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