Jang-Woo Ryu
According to our database1,
Jang-Woo Ryu
authored at least 4 papers
between 2011 and 2024.
Collaborative distances:
Collaborative distances:
Timeline
2012
2014
2016
2018
2020
2022
2024
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Book In proceedings Article PhD thesis Dataset OtherLinks
On csauthors.net:
Bibliography
2024
13.2 A 32Gb 8.0Gb/s/pin DDR5 SDRAM with a Symmetric-Mosaic Architecture in a 5<sup>th</sup>-Generation 10nm DRAM Process.
Proceedings of the IEEE International Solid-State Circuits Conference, 2024
2014
25.1 A 3.2Gb/s/pin 8Gb 1.0V LPDDR4 SDRAM with integrated ECC engine for sub-1V DRAM core operation.
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014
2012
A 1.2 V 12.8 GB/s 2 Gb Mobile Wide-I/O DRAM With 4 × 128 I/Os Using TSV Based Stacking.
IEEE J. Solid State Circuits, 2012
2011
Proceedings of the IEEE International Solid-State Circuits Conference, 2011