Janakiraman Viraraghavan

According to our database, Janakiraman Viraraghavan authored at least 14 papers between 2008 and 2024.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2024

Input-Conditioned Quantisation for ENOB Improvement in CIM ADC Columns Targeting Large-Length Partial Sums.

S. Ashwin Balagopal, Janakiraman Viraraghavan, Balaji Vijayakumar

IEEE Trans. Circuits Syst. II Express Briefs, June, 2024

2023

Geometric Programming Approach to Glitch Minimization via Gate Sizing.

Karthikeyan Muthamizh Vithagan, Vignesh Sundaresha, Janakiraman Viraraghavan

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., June, 2023

Layout-Based Digital IC Course Projects in Large Classes: Implementation, Evaluation, and Plagiarism Detection.

Alfred Festus Davidson, Janakiraman Viraraghavan

IEEE Trans. Educ., February, 2023

2021

An Area-Efficient Word-Line Pitch-Aligned 8T SRAM Compatible Digital-to-Analog Converter.

Balaji Vijayakumar, Janakiraman Viraraghavan

Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

2020

Statistical compact model extraction for skew-normal distributions.

Koduru Revanth, Janakiraman Viraraghavan

IET Circuits Devices Syst., 2020

Flash Based In-Memory Multiply-Accumulate Realisation: A Theoretical Study.

S. Ashwin Balagopal, Janakiraman Viraraghavan

Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

2018

80-kb Logic Embedded High-K Charge Trap Transistor-Based Multi-Time-Programmable Memory With No Added Process Complexity.

Balaji Jayaraman, Derek Leu, Janakiraman Viraraghavan, Alberto Cestero, Ming Yin, John Golz, Rajesh Reddy Tummuru, Ramesh Raghavan, Dan Moy, Thejas Kempanna, Faraz Khan, Toshiaki Kirihata, Subramanian S. Iyer

IEEE J. Solid State Circuits, 2018

2016

A 14 nm 1.1 Mb Embedded DRAM Macro With 1 ns Access.

Gregory Fredeman, Donald W. Plass, Abraham Mathews, Janakiraman Viraraghavan, Kenneth Reyer, Thomas J. Knips, Thomas Miller, Elizabeth L. Gerhard, Dinesh Kannambadi, Chris Paone, Dongho Lee, Daniel Rainey, Michael A. Sperling, Michael Whalen, Steven Burns, Rajesh Reddy Tummuru, Herbert Ho, Alberto Cestero, Norbert Arnold, Babar A. Khan, Toshiaki Kirihata, Subramanian S. Iyer

IEEE J. Solid State Circuits, 2016

80Kb 10ns read cycle logic Embedded High-K charge trap Multi-Time-Programmable Memory scalable to 14nm FIN with no added process complexity.

Janakiraman Viraraghavan, Derek Leu, Balaji Jayaraman, Alberto Cestero, Robert Kilker, Ming Yin, John Golz, Rajesh Reddy Tummuru, Ramesh Raghavan, Dan Moy, Thejas Kempanna, Faraz Khan, Toshiaki Kirihata, Subramanian S. Iyer

Proceedings of the 2016 IEEE Symposium on VLSI Circuits, 2016

2012

Statistical Compact Model Extraction: A Neural Network Approach.

Janakiraman Viraraghavan, Shrinivas J. Pandharpure, Josef Watts

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012

2010

Voltage and Temperature Aware Statistical Leakage Analysis Framework Using Artificial Neural Networks.

Janakiraman Viraraghavan, Bharadwaj Amrutur, V. Visvanathan

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010

2008

Voltage and Temperature Scalable Logic Cell Leakage Models Considering Local Variations Based on Transistor Stacks.

Janakiraman Viraraghavan, Bharadwaj Amrutur, V. Visvanathan

J. Low Power Electron., 2008

Voltage and Temperature Scalable Standard Cell Leakage Models Based on Stacks for Statistical Leakage Characterization.

Janakiraman Viraraghavan, Bishnu Prasad Das, Bharadwaj Amrutur

Proceedings of the 21st International Conference on VLSI Design (VLSI Design 2008), 2008

Voltage and Temperature Scalable Gate Delay and Slew Models Including Intra-Gate Variations.

Bishnu Prasad Das, Janakiraman Viraraghavan, Bharadwaj Amrutur, H. S. Jamadagni, N. V. Arvind

Proceedings of the 21st International Conference on VLSI Design (VLSI Design 2008), 2008