Janak Sharda
Orcid: 0000-0002-1438-2439
According to our database1,
Janak Sharda
authored at least 9 papers
between 2019 and 2024.
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Bibliography
2024
Thermally Constrained Codesign of Heterogeneous 3-D Integration of Compute-in-Memory, Digital ML Accelerator, and RISC-V Cores for Mixed ML and Non-ML Workloads.
IEEE Trans. Very Large Scale Integr. Syst., September, 2024
Impact of In-Pixel Processing Circuit Non-idealities on Multi-object Tracking Accuracy for Autonomous Driving.
Proceedings of the 67th IEEE International Midwest Symposium on Circuits and Systems, 2024
Proceedings of the 6th IEEE International Conference on AI Circuits and Systems, 2024
2023
Temporal Frame Filtering for Autonomous Driving Using 3D-Stacked Global Shutter CIS With IWO Buffer Memory and Near-Pixel Compute.
IEEE Trans. Circuits Syst. I Regul. Pap., May, 2023
2022
On-chip learning of a domain-wall-synapse-crossbar-array-based convolutional neural network.
Neuromorph. Comput. Eng., 2022
Proceedings of the 4th IEEE International Conference on Artificial Intelligence Circuits and Systems, 2022
2021
A Crossbar Array of Analog-Digital-Hybrid Volatile Memory Synapse Cells for Energy-Efficient On-Chip Learning.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021
2020
Reduction of the Weight-Decay Rate of Volatile Memory Synapses in an Analog Hardware Neural Network for Accurate and Scalable On-Chip Learning.
Proceedings of the International Conference on Neuromorphic Systems, 2020
2019
On-chip Learning In A Conventional Silicon MOSFET Based Analog Hardware Neural Network.
Proceedings of the 2019 IEEE Biomedical Circuits and Systems Conference, 2019