Janak H. Patel

According to our database, Janak H. Patel authored at least 177 papers between 1976 and 2005.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of three.

2005

Hardware Ef.cient LBISTWith Complementary Weights.

Liyang Lai, Janak H. Patel, Thomas Rinderknecht, Wu-Tung Cheng

Proceedings of the 23rd International Conference on Computer Design (ICCD 2005), 2005

2004

Partial Scan Design Based on Circuit State Information and Functional Analysis.

Dong Xiang, Janak H. Patel

IEEE Trans. Computers, 2004

What Does Robust Testing a Subset of Paths, Tell us about the Untested Paths in the Circuit?

Manish Sharma, Janak H. Patel

Proceedings of the 22nd IEEE VLSI Test Symposium (VTS 2004), 2004

Logic BIST Using Constrained Scan Cells.

Liyang Lai, Thomas Rinderknecht, Wu-Tung Cheng, Janak H. Patel

Proceedings of the 22nd IEEE VLSI Test Symposium (VTS 2004), 2004

Logic BIST with Scan Chain Segmentation.

Liyang Lai, Janak H. Patel, Thomas Rinderknecht, Wu-Tung Cheng

Proceedings of the Proceedings 2004 International Test Conference (ITC 2004), 2004

Enhancement of the Illinois Scan Architecture for Use with Multiple Scan Inputs.

Mihir A. Shah, Janak H. Patel

Proceedings of the 2004 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2004), 2004

The evolution of dependable computing at the University of Illinois.

Ravishankar K. Iyer, William H. Sanders, Janak H. Patel, Zbigniew Kalbarczyk

Proceedings of the Building the Information Society, 2004

2003

Test Data Compression and Test Time Reduction of Longest-Path-Per-Gate Tests based on Illinois Scan Architecture.

Manish Sharma, Janak H. Patel, Jeff Rearick

Proceedings of the 21st IEEE VLSI Test Symposium (VTS 2003), 27 April, 2003

Application of Saluja-Karpovsky Compactors to Test Responses with Many Unknowns.

Janak H. Patel, Steven S. Lumetta, Sudhakar M. Reddy

Proceedings of the 21st IEEE VLSI Test Symposium (VTS 2003), 27 April, 2003

2002

Reconfiguration Technique for Reducing Test Time and Test Data Volume in Illinois Scan Architecture Based Designs .

Amit R. Pandey, Janak H. Patel

Proceedings of the 20th IEEE VLSI Test Symposium (VTS 2002), Without Testing It's a Gamble, 28 April, 2002

Finding a Small Set of Longest Testable Paths that Cover Every Gate.

Manish Sharma, Janak H. Patel

Proceedings of the Proceedings IEEE International Test Conference 2002, 2002

An Incremental Algorithm for Test Generation in Illinois Scan Architecture Based Designs.

Amit R. Pandey, Janak H. Patel

Proceedings of the 2002 Design, 2002

2001

Diagnostic simulation of stuck-at faults in sequential circuits using compact lists.

Ismed Hartanto, Srikanth Venkataraman, W. Kent Fuchs, Elizabeth M. Rudnick, Janak H. Patel, Sreejit Chakravarty

ACM Trans. Design Autom. Electr. Syst., 2001

A Graph Traversal Based Framework For Sequential Logic Implication With An Application To C-Cycle Redundancy Identification.

Jian-Kun Zhao, Jeffrey A. Newquist, Janak H. Patel

Proceedings of the 14th International Conference on VLSI Design (VLSI Design 2001), 2001

Testing of critical paths for delay faults.

Manish Sharma, Janak H. Patel

Proceedings of the Proceedings IEEE International Test Conference 2001, Baltimore, MD, USA, 30 October, 2001

A case study on the implementation of the Illinois Scan Architecture.

Frank F. Hsu, Kenneth M. Butler, Janak H. Patel

Proceedings of the Proceedings IEEE International Test Conference 2001, Baltimore, MD, USA, 30 October, 2001

2000

Peak power estimation of VLSI circuits: new peak power measures.

Michael S. Hsiao, Elizabeth M. Rudnick, Janak H. Patel

IEEE Trans. Very Large Scale Integr. Syst., 2000

Dynamic state traversal for sequential circuit test generation.

Michael S. Hsiao, Elizabeth M. Rudnick, Janak H. Patel

ACM Trans. Design Autom. Electr. Syst., 2000

Test set compaction algorithms for combinational circuits.

Ilker Hamzaoglu, Janak H. Patel

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2000

Bounding Circuit Delay by Testing a Very Small Subset of Paths.

Manish Sharma, Janak H. Patel

Proceedings of the 18th IEEE VLSI Test Symposium (VTS 2000), 30 April, 2000

Reducing Test Application Time for Built-in-Self-Test Test Pattern Generators.

Ilker Hamzaoglu, Janak H. Patel

Proceedings of the 18th IEEE VLSI Test Symposium (VTS 2000), 30 April, 2000

Enhanced delay defect coverage with path-segments.

Manish Sharma, Janak H. Patel

Proceedings of the Proceedings IEEE International Test Conference 2000, 2000

Deterministic Test Pattern Generation Techniques for Sequential Circuits.

Ilker Hamzaoglu, Janak H. Patel

Proceedings of the 2000 IEEE/ACM International Conference on Computer-Aided Design, 2000

1999

Efficient Techniques for Dynamic Test Sequence Compaction.

Elizabeth M. Rudnick, Janak H. Patel

IEEE Trans. Computers, 1999

Fast Static Compaction Algorithms for Sequential Circuit Test Vectors.

Michael S. Hsiao, Elizabeth M. Rudnick, Janak H. Patel

IEEE Trans. Computers, 1999

New Techniques for Deterministic Test Pattern Generation.

Ilker Hamzaoglu, Janak H. Patel

J. Electron. Test., 1999

An Approach to Evaluating the Effects of Realistic Faults in Digital Circuits.

Zbigniew Kalbarczyk, Janak H. Patel, Myeong S. Lee, Ravishankar K. Iyer

Proceedings of the 12th International Conference on VLSI Design (VLSI Design 1999), 1999

A Test Generator for Segment Delay Faults.

Keerthi Heragu, Janak H. Patel, Vishwani D. Agrawal

Proceedings of the 12th International Conference on VLSI Design (VLSI Design 1999), 1999

Reducing Test Application Time for Full Scan Embedded Cores.

Ilker Hamzaoglu, Janak H. Patel

Proceedings of the Digest of Papers: FTCS-29, 1999

1998

Application of genetically engineered finite-state-machine sequences to sequential circuit ATPG.

Michael S. Hsiao, Elizabeth M. Rudnick, Janak H. Patel

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1998

High-Level Controllability and Observability Analysis for Test Synthesis.

Frank F. Hsu, Janak H. Patel

J. Electron. Test., 1998

Diagnostic Simulation of Sequential Circuits Using Fault Sampling.

Srikanth Venkataraman, W. Kent Fuchs, Janak H. Patel

Proceedings of the 11th International Conference on VLSI Design (VLSI Design 1991), 1998

Partial Scan Selection Based on Dynamic Reachability and Observability Information.

Michael S. Hsiao, Gurjeet S. Saund, Elizabeth M. Rudnick, Janak H. Patel

Proceedings of the 11th International Conference on VLSI Design (VLSI Design 1991), 1998

Compact two-pattern test set generation for combinational and full scan circuits.

Ilker Hamzaoglu, Janak H. Patel

Proceedings of the Proceedings IEEE International Test Conference 1998, 1998

Stuck-at fault: a fault model for the next millennium.

Janak H. Patel

Proceedings of the Proceedings IEEE International Test Conference 1998, 1998

Retrospective: A Low-Overhead Coherence Solution for Multiprocessors with Private Cache Memories.

Janak H. Patel

Proceedings of the 25 Years of the International Symposia on Computer Architecture (Selected Papers)., 1998

Retrospective: Improving the Throughput of a Pipeline by Insertion of Delays.

Janak H. Patel

Proceedings of the 25 Years of the International Symposia on Computer Architecture (Selected Papers)., 1998

Enhancing topological ATPG with high-level information and symbolic techniques.

Fulvio Corno, Janak H. Patel, Elizabeth M. Rudnick, Matteo Sonza Reorda, Roberto Vietti

Proceedings of the International Conference on Computer Design: VLSI in Computers and Processors, 1998

High-level variable selection for partial-scan implementation.

Frank F. Hsu, Janak H. Patel

Proceedings of the 1998 IEEE/ACM International Conference on Computer-Aided Design, 1998

1997

Algorithms to compute bridging fault coverage of <i>I_DDQ</i> test sets.

Paul J. Thadikaran, Sreejit Chakravarty, Janak H. Patel

ACM Trans. Design Autom. Electr. Syst., 1997

A genetic algorithm framework for test generation.

Elizabeth M. Rudnick, Janak H. Patel, Gary S. Greenstein, Thomas M. Niermann

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1997

Improving a nonenumerative method to estimate path delay fault coverage.

Keerthi Heragu, Vishwani D. Agrawal, Michael L. Bushnell, Janak H. Patel

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1997

Design for Testability Using State Distances.

Frank F. Hsu, Janak H. Patel

J. Electron. Test., 1997

Static logic implication with application to redundancy identification.

Jian-Kun Zhao, Elizabeth M. Rudnick, Janak H. Patel

Proceedings of the 15th IEEE VLSI Test Symposium (VTS'97), 1997

SPITFIRE: scalable parallel algorithms for test set partitioned fault simulation.

Dilip Krishnaswamy, Elizabeth M. Rudnick, Janak H. Patel, Prithviraj Banerjee

Proceedings of the 15th IEEE VLSI Test Symposium (VTS'97), 1997

Fast Algorithms for Static Compaction of Sequential Circuit Test Vectors.

Michael S. Hsiao, Elizabeth M. Rudnick, Janak H. Patel

Proceedings of the 15th IEEE VLSI Test Symposium (VTS'97), 1997

Diagnostic Test Pattern Generation for Sequential Circuits.

Ismed Hartanto, Vamsi Boppana, Janak H. Patel, W. Kent Fuchs

Proceedings of the 15th IEEE VLSI Test Symposium (VTS'97), 1997

Overcoming the Serial Logic Simulation Bottleneck in Parallel Fault Simulation.

Elizabeth M. Rudnick, Janak H. Patel

Proceedings of the 10th International Conference on VLSI Design (VLSI Design 1997), 1997

Parallel Genetic Algorithms for Simulation-Based Sequential Circuit Test Generation.

Dilip Krishnaswamy, Michael S. Hsiao, Vikram Saxena, Elizabeth M. Rudnick, Janak H. Patel, Prithviraj Banerjee

Proceedings of the 10th International Conference on VLSI Design (VLSI Design 1997), 1997

Dynamic Fault Grouping for PROOFS: A Win for Large Sequential Circuits.

Charles R. Graham, Elizabeth M. Rudnick, Janak H. Patel

Proceedings of the 10th International Conference on VLSI Design (VLSI Design 1997), 1997

Asynchronous Parallel Algorithms for Test Set Partitioned Fault Simulation.

Dilip Krishnaswamy, Prithviraj Banerjee, Elizabeth M. Rudnick, Janak H. Patel

Proceedings of the Eleventh Workshop on Parallel and Distributed Simulation, 1997

Putting the Squeeze on Test Sequences.

Elizabeth M. Rudnick, Janak H. Patel

Proceedings of the Proceedings IEEE International Test Conference 1997, 1997

BART: A Bridging Fault Test Generation for Sequential Circuits.

James P. Cusey, Janak H. Patel

Proceedings of the Proceedings IEEE International Test Conference 1997, 1997

K2: an estimator for peak sustainable power of VLSI circuits.

Michael S. Hsiao, Elizabeth M. Rudnick, Janak H. Patel

Proceedings of the 1997 International Symposium on Low Power Electronics and Design, 1997

Effects of delay models on peak power estimation of VLSI sequential circuits.

Michael S. Hsiao, Elizabeth M. Rudnick, Janak H. Patel

Proceedings of the 1997 IEEE/ACM International Conference on Computer-Aided Design, 1997

Fast identification of untestable delay faults using implications.

Keerthi Heragu, Janak H. Patel, Vishwani D. Agrawal

Proceedings of the 1997 IEEE/ACM International Conference on Computer-Aided Design, 1997

Partial Scan beyond Cycle Cutting.

Gurjeet S. Saund, Michael S. Hsiao, Janak H. Patel

Proceedings of the Digest of Papers: FTCS-27, 1997

Sequential circuit test generation using dynamic state traversal.

Michael S. Hsiao, Elizabeth M. Rudnick, Janak H. Patel

Proceedings of the European Design and Test Conference, 1997

1996

Hierarchical test generation under architectural level functional constraints.

Jaushin Lee, Janak H. Patel

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1996

A Gate-Level Simulation Environment for Alpha-Particle-Induced Transient Faults.

Hungse Cha, Elizabeth M. Rudnick, Janak H. Patel, Ravishankar K. Iyer, Gwan S. Choi

IEEE Trans. Computers, 1996

Genetic-algorithm-based test generation for current testing of bridging faults in CMOS VLSI circuits.

Terry Lee, Ibrahim N. Hajj, Elizabeth M. Rudnick, Janak H. Patel

Proceedings of the 14th IEEE VLSI Test Symposium (VTS'96), April 28, 1996

Automatic test generation using genetically-engineered distinguishing sequences.

Michael S. Hsiao, Elizabeth M. Rudnick, Janak H. Patel

Proceedings of the 14th IEEE VLSI Test Symposium (VTS'96), April 28, 1996

Segment delay faults: a new fault model.

Keerthi Heragu, Janak H. Patel, Vishwani D. Agrawal

Proceedings of the 14th IEEE VLSI Test Symposium (VTS'96), April 28, 1996

Improving accuracy in path delay fault coverage estimation.

Keerthi Heragu, Janak H. Patel, Vishwani D. Agrawal

Proceedings of the 9th International Conference on VLSI Design (VLSI Design 1996), 1996

A Global Algorithm for the Partial Scan Design Problem Using Circuit State Information.

Dong Xiang, Janak H. Patel

Proceedings of the Proceedings IEEE International Test Conference 1996, 1996

On Potential Fault Detection in Sequential Circuits.

Elizabeth M. Rudnick, Janak H. Patel, Irith Pomeranz

Proceedings of the Proceedings IEEE International Test Conference 1996, 1996

Testability Insertion in Behavioral Descriptions.

Frank F. Hsu, Elizabeth M. Rudnick, Janak H. Patel

Proceedings of the 9th International Symposium on System Synthesis, 1996

Simulation-based techniques for dynamic test sequence compaction.

Elizabeth M. Rudnick, Janak H. Patel

Proceedings of the 1996 IEEE/ACM International Conference on Computer-Aided Design, 1996

Enhancing high-level control-flow for improved testability.

Frank F. Hsu, Elizabeth M. Rudnick, Janak H. Patel

Proceedings of the 1996 IEEE/ACM International Conference on Computer-Aided Design, 1996

SIGMA: a simulator for segment delay faults.

Keerthi Heragu, Janak H. Patel, Vishwani D. Agrawal

Proceedings of the 1996 IEEE/ACM International Conference on Computer-Aided Design, 1996

On Double Transition Faults as a Delay Fault Model.

Irith Pomeranz, Sudhakar M. Reddy, Janak H. Patel

Proceedings of the 6th Great Lakes Symposium on VLSI (GLS-VLSI '96), 1996

Alternating Strategies for Sequential Circuit ATPG.

Michael S. Hsiao, Elizabeth M. Rudnick, Janak H. Patel

Proceedings of the 1996 European Design and Test Conference, 1996

Partial Scan Design Based on Circuit State Information.

Dong Xiang, Srikanth Venkataraman, W. Kent Fuchs, Janak H. Patel

Proceedings of the 33st Conference on Design Automation, 1996

1995

Sequential circuit testability enhancement using a nonscan approach.

Elizabeth M. Rudnick, Vivek Chickermane, Prithviraj Banerjee, Janak H. Patel

IEEE Trans. Very Large Scale Integr. Syst., 1995

A distance reduction approach to design for testability.

Frank F. Hsu, Janak H. Patel

Proceedings of the 13th IEEE VLSI Test Symposium (VTS'95), April 30, 1995

Cyclic stress tests for full scan circuits.

Vinay Dabholkar, Sreejit Chakravarty, J. Najm, Janak H. Patel

Proceedings of the 13th IEEE VLSI Test Symposium (VTS'95), April 30, 1995

A genetic approach to test application time reduction for full scan and partial scan circuits.

Elizabeth M. Rudnick, Janak H. Patel

Proceedings of the 8th International Conference on VLSI Design (VLSI Design 1995), 1995

A parallel algorithm for fault simulation based on PROOFS .

Steven Parkes, Prithviraj Banerjee, Janak H. Patel

Proceedings of the 1995 International Conference on Computer Design (ICCD '95), 1995

A new architectural-level fault simulation using propagation prediction of grouped fault-effects.

Michael S. Hsiao, Janak H. Patel

Proceedings of the 1995 International Conference on Computer Design (ICCD '95), 1995

Fault Simulation of<i>I_DDQ</i> Tests for Bridging Faults in Sequential Circuits.

Paul J. Thadikaran, Sreejit Chakravarty, Janak H. Patel

Proceedings of the Digest of Papers: FTCS-25, 1995

Rapid Diagnostic Fault Simulation of Stuck-at Faults in Sequential Circuits Using Compact Lists.

Srikanth Venkataraman, Ismed Hartanto, W. Kent Fuchs, Elizabeth M. Rudnick, Sreejit Chakravarty, Janak H. Patel

Proceedings of the 32st Conference on Design Automation, 1995

Combining Deterministic and Genetic Approaches for Sequential Circuit Test Generation.

Elizabeth M. Rudnick, Janak H. Patel

Proceedings of the 32st Conference on Design Automation, 1995

Overhead reduction techniques for hierarchical fault simulation.

Eiji Harada, Janak H. Patel

Proceedings of the 4th Asian Test Symposium (ATS '95), 1995

1994

An observability enhancement approach for improved testability and at-speed test.

Elizabeth M. Rudnick, Vivek Chickermane, Janak H. Patel

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1994

Architectural level test generation for microprocessors.

Jaushin Lee, Janak H. Patel

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1994

Addressing design for testability at the architectural level.

Vivek Chickermane, Jaushin Lee, Janak H. Patel

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1994

Hybrid Resource Management Algorithms for Multicomputer Systems.

Jeff Baxter, John W. C. Fu, Balkrishna Ramkumar, Janak H. Patel

Proceedings of the 8th International Symposium on Parallel Processing, 1994

Latch Design for Transient Pulse Tolerance.

Hungse Cha, Janak H. Patel

Proceedings of the Proceedings 1994 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1994

Fast timing simulation of transient faults in digital circuits.

Abhijit Dharchoudhury, Sung-Mo Kang, Hungse Cha, Janak H. Patel

Proceedings of the 1994 IEEE/ACM International Conference on Computer-Aided Design, 1994

Trace Driven Simulation using Sampled Traces.

John W. C. Fu, Janak H. Patel

Proceedings of the 27th Annual Hawaii International Conference on System Sciences (HICSS-27), 1994

Application of Simple Genetic Algorithms to Sequential Circuit Test Generation.

Elizabeth M. Rudnick, John G. Holm, Daniel G. Saab, Janak H. Patel

Proceedings of the EDAC - The European Conference on Design Automation, ETC - European Test Conference, EUROASIC - The European Event in ASIC Design, Proceedings, February 28, 1994

Sequential Circuit Test Generation in a Genetic Algorithm Framework.

Elizabeth M. Rudnick, Janak H. Patel, Gary S. Greenstein, Thomas M. Niermann

Proceedings of the 31st Conference on Design Automation, 1994

ProperHITEC: A Portable, Parallel, Object-Oriented Approach to Sequential Test Generation.

Steven Parkes, Prithviraj Banerjee, Janak H. Patel

Proceedings of the 31st Conference on Design Automation, 1994

Microprocessor Testing: Which Technique is Best? (Panel).

Jacob A. Abraham, Sandip Kundu, Janak H. Patel, Manuel A. d'Abreu, Bulent I. Dervisoglu, Marc E. Levitt, Hector R. Sucar, Ron G. Walther

Proceedings of the 31st Conference on Design Automation, 1994

1993

NETRA: A Hierarchical and Partitionable Architecture for Computer Vision Systems.

Alok N. Choudhary, Janak H. Patel, Narendra Ahuja

IEEE Trans. Parallel Distributed Syst., 1993

An architectural level test generator based on nonlinear equation solving.

Jaushin Lee, Janak H. Patel

J. Electron. Test., 1993

Testability analysis based on structural and behavioral information.

Jaushin Lee, Janak H. Patel

Proceedings of the 11th IEEE VLSI Test Symposium (VTS'93), 1993

Impact of high level functional constraints on testability.

Jaushin Lee, Vivek Chickermane, Janak H. Patel

Proceedings of the 11th IEEE VLSI Test Symposium (VTS'93), 1993

Fast and Accurate CMOS Bridging Fault Simulation.

Jeff Rearick, Janak H. Patel

Proceedings of the Proceedings IEEE International Test Conference 1993, Designing, Testing, and Diagnostics, 1993

Efficient Variable Ordering Heuristics for Shared ROBDD.

Pi-Yu Chung, Ibrahim N. Hajj, Janak H. Patel

Proceedings of the 1993 IEEE International Symposium on Circuits and Systems, 1993

Memory Reference Behavior of Compiler Optimized Programs on High Speed.

John W. C. Fu, Janak H. Patel

Proceedings of the 1993 International Conference on Parallel Processing, 1993

A Logic-Level Model for alpha-Paricle Hits in CMOS Circuits.

Hungse Cha, Janak H. Patel

Proceedings of the Proceedings 1993 International Conference on Computer Design: VLSI in Computers & Processors, 1993

Theory and Practice of Sequential Machine Testing and Testability.

Irith Pomeranz, Sudhakar M. Reddy, Janak H. Patel

Proceedings of the Digest of Papers: FTCS-23, 1993

A Fast and Accurate Gate-Level Transient Fault Simulation Environment.

Hungse Cha, Elizabeth M. Rudnick, Gwan S. Choi, Janak H. Patel, Ravishankar K. Iyer

Proceedings of the Digest of Papers: FTCS-23, 1993

Non-Scan Design-for-Testability Techniques for Sequential Circuits.

Vivek Chickermane, Elizabeth M. Rudnick, Prithviraj Banerjee, Janak H. Patel

Proceedings of the 30th Design Automation Conference. Dallas, 1993

1992

Test compaction for sequential circuits.

Thomas M. Niermann, Rabindra K. Roy, Janak H. Patel, Jacob A. Abraham

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1992

PROOFS: a fast, memory-efficient sequential circuit fault simulator.

Thomas M. Niermann, Wu-Tung Cheng, Janak H. Patel

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1992

An efficient design of embedded memories and their testability analysis using Markov chains.

Pinaki Mazumder, Janak H. Patel

J. Electron. Test., 1992

Probe point insertion for at-speed test.

Elizabeth M. Rudnick, Vivek Chickermane, Janak H. Patel

Proceedings of the 10th IEEE VLSI Test Symposium (VTS'92), 1992

Stride directed prefetching in scalar processors.

John W. C. Fu, Janak H. Patel, Bob L. Janssens

Proceedings of the 25th Annual International Symposium on Microarchitecture, 1992

Diagnostic Fault Simulation of Sequential Circuits.

Elizabeth M. Rudnick, W. Kent Fuchs, Janak H. Patel

Proceedings of the Proceedings IEEE International Test Conference 1992, 1992

An Instruction Sequence Assembling Methodology for Testing Microprocessors.

Jaushin Lee, Janak H. Patel

Proceedings of the Proceedings IEEE International Test Conference 1992, 1992

Design for Testability Using Architectural Descriptions.

Vivek Chickermane, Jaushin Lee, Janak H. Patel

Proceedings of the Proceedings IEEE International Test Conference 1992, 1992

Profiling Based Task Migration.

Jeff Baxter, Janak H. Patel

Proceedings of the 6th International Parallel Processing Symposium, 1992

Compile Time Parallel Resource Allocation for Unbounded Tree Structure Task Graphs.

Jeff Baxter, Balkrishna Ramkumar, Janak H. Patel

Proceedings of the 1992 International Conference on Parallel Processing, 1992

Automatic test generation for linear digital systems with bi-level search using matrix transform methods.

Rabindra K. Roy, Abhijit Chatterjee, Janak H. Patel, Jacob A. Abraham, Manuel A. d'Abreu

Proceedings of the 1992 IEEE/ACM International Conference on Computer-Aided Design, 1992

E-PROOFS: a CMOS bridging fault simulator.

Gary S. Greenstein, Janak H. Patel

Proceedings of the 1992 IEEE/ACM International Conference on Computer-Aided Design, 1992

A comparative study of design for testability methods using high-level and gate-level descriptions.

Vivek Chickermane, Jaushin Lee, Janak H. Patel

Proceedings of the 1992 IEEE/ACM International Conference on Computer-Aided Design, 1992

Hierarchical Test Generation under Intensive Global Functional Constraints.

Jaushin Lee, Janak H. Patel

Proceedings of the 29th Design Automation Conference, 1992

APT: An Area-Performance-Testability Driven Placement Algorithm.

Sungho Kim, Prithviraj Banerjee, Vivek Chickermane, Janak H. Patel

Proceedings of the 29th Design Automation Conference, 1992

1991

Efficient testing strategies for bit- and digit-serial arrays used in digital signal processors.

Abhijit Chatterjee, Rabindra K. Roy, Jacob A. Abraham, Janak H. Patel

Digit. Signal Process., 1991

ARTEST: An Architectural Level Test Generator for Data Path Faults and Control Faults.

Jaushin Lee, Janak H. Patel

Proceedings of the Proceedings IEEE International Test Conference 1991, 1991

Data Prefetching in Multiprocessor Vector Cache Memories.

John W. C. Fu, Janak H. Patel

Proceedings of the 18th Annual International Symposium on Computer Architecture. Toronto, 1991

Data Prefetching Strategies for Vector Cache Memories.

John W. C. Fu, Janak H. Patel

Proceedings of the Fifth International Parallel Processing Symposium, Proceedings, Anaheim, California, USA, April 30, 1991

How Do We Make Parallel Processing a Reality? Bridging the Gap Between Theory and Practice.

Alfred Brenner, Richard F. Freund, R. Stockton Gaines, Rob Kelly, Louis Lome, Richard McAndrew, Alexandru Nicolau, Janak H. Patel, Thomas Probert, John H. Reif, Jorge L. C. Sanz, Howard Jay Siegel, Jon A. Webb

Proceedings of the Fifth International Parallel Processing Symposium, Proceedings, Anaheim, California, USA, April 30, 1991

Methods for Reducing Events in Sequential Circuit Fault Simulation.

Elizabeth M. Rudnick, Thomas M. Niermann, Janak H. Patel

Proceedings of the 1991 IEEE/ACM International Conference on Computer-Aided Design, 1991

A Signal-Driven Discrete Relaxation Technique for Architectural Level Test Generation.

Jaushin Lee, Janak H. Patel

Proceedings of the 1991 IEEE/ACM International Conference on Computer-Aided Design, 1991

A Fault Oriented Partial Scan Design Approach.

Vivek Chickermane, Janak H. Patel

Proceedings of the 1991 IEEE/ACM International Conference on Computer-Aided Design, 1991

An Architectural Level Test Generator for a Hierarchical Design Environment.

Jaushin Lee, Janak H. Patel

Proceedings of the 1991 International Symposium on Fault-Tolerant Computing, 1991

HITEC: a test generation package for sequential circuits.

Thomas M. Niermann, Janak H. Patel

Proceedings of the conference on European design automation, 1991

Parallel Test Generation for Sequential Circuits on General-Purpose Multiprocessors.

Srinivas Patil, Prithviraj Banerjee, Janak H. Patel

Proceedings of the 28th Design Automation Conference, 1991

1990

Error Recovery in Shared Memory Multiprocessors Using Private Caches.

Kun-Lung Wu, W. Kent Fuchs, Janak H. Patel

IEEE Trans. Parallel Distributed Syst., 1990

An optimization based approach to the partial scan design problem.

Vivek Chickermane, Janak H. Patel

Proceedings of the Proceedings IEEE International Test Conference 1990, 1990

Parallel implementation and evaluation of motion estimation system algorithms on a distributed memory multiprocessor using knowledge based mappings.

Alok N. Choudhary, Mun K. Leung, Thomas S. Huang, Janak H. Patel

Proceedings of the 10th IAPR International Conference on Pattern Recognition, 1990

A reconfigurable and hierarchical parallel processing architecture: performance results for stereo vision.

Alok N. Choudhary, Subhodev Das, Narendra Ahuja, Janak H. Patel

Proceedings of the 10th IAPR International Conference on Pattern Recognition, 1990

Performance Evaluation of Clusters of NETRA: An Architecture for Computer Vision Systems.

Alok N. Choudhary, Janak H. Patel

Proceedings of the 1990 International Conference on Parallel Processing, 1990

PROOFS: a super fast fault simulator for sequential circuits.

Wu-Tung Cheng, Janak H. Patel

Proceedings of the European Design Automation Conference, 1990

1989

Experimental evaluation of testability measures for test generation (logic circuits).

Susheel J. Chandra, Janak H. Patel

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1989

Parallel Testing for Pattern-Sensitive Faults in Semiconductor Random-Access Memories.

Pinaki Mazumder, Janak H. Patel

IEEE Trans. Computers, 1989

Diagnosis and Repair of Memory with Coupling Faults.

Ming-Feng Chang, W. Kent Fuchs, Janak H. Patel

IEEE Trans. Computers, 1989

Load balancing and task decomposition techniques for parallel implementation of integrated vision systems algorithms.

Alok N. Choudhary, Janak H. Patel

Proceedings of the Proceedings Supercomputing '89, Reno, NV, USA, November 12-17, 1989, 1989

Cache-Based Error Recovery for Shared Memory Multiprocessor Systems.

Kun-Lung Wu, W. Kent Fuchs, Janak H. Patel

Proceedings of the International Conference on Parallel Processing, 1989

The LAST Algorithm: A Heuristic-Based Static Task Allocation Algorithm.

Jeff Baxter, Janak H. Patel

Proceedings of the International Conference on Parallel Processing, 1989

Accurate logic simulation in the presence of unknowns.

Susheel J. Chandra, Janak H. Patel

Proceedings of the 1989 IEEE International Conference on Computer-Aided Design, 1989

A Functional-Level Test Generation Methodology Using Two-level Representations.

Utpal J. Davé, Janak H. Patel

Proceedings of the 26th ACM/IEEE Design Automation Conference, 1989

1988

Methodologies for testing embedded content addressable memories.

Pinaki Mazumder, Janak H. Patel, W. Kent Fuchs

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1988

Accurate Low-Cost Methods for Performance Evaluation of Cache Memory Systems.

Subhasis Laha, Janak H. Patel, Ravishankar K. Iyer

IEEE Trans. Computers, 1988

Performance Evaluation of On-Chip Register and Cache Organizations.

Richard J. Eickemeyer, Janak H. Patel

Proceedings of the 15th Annual International Symposium on Computer Architecture, 1988

A Parallel Processing Architecture for an Integrated Vision System.

Alok N. Choudhary, Janak H. Patel

Proceedings of the International Conference on Parallel Processing, 1988

Test generation in a parallel processing environment.

Susheel J. Chandra, Janak H. Patel

Proceedings of the Computer Design: VLSI in Computers and Processors, 1988

Compaction of ATPG-generated test sequences for sequential circuits.

Rabindra K. Roy, Thomas M. Niermann, Janak H. Patel, Jacob A. Abraham, Resve A. Saleh

Proceedings of the 1988 IEEE International Conference on Computer-Aided Design, 1988

1987

A Minimum Test Set for Multiple Fault Detection in Ripple Carry Adders.

Wu-Tung Cheng, Janak H. Patel

IEEE Trans. Computers, 1987

Performance Evaluation of Multiple Register Sets.

Richard J. Eickemeyer, Janak H. Patel

Proceedings of the 14th Annual International Symposium on Computer Architecture. Pittsburgh, 1987

Parallel Garbage Collection on a Virtual Memory System.

Santosh G. Abraham, Janak H. Patel

Proceedings of the International Conference on Parallel Processing, 1987

Design and Algorithms for Parallel Testing of Random Access and Content Addressable Memories.

Pinaki Mazumder, Janak H. Patel, W. Kent Fuchs

Proceedings of the 24th ACM/IEEE Design Automation Conference. Miami Beach, FL, USA, June 28, 1987

A Hierarchical Approach Test Vector Generation.

Susheel J. Chandra, Janak H. Patel

Proceedings of the 24th ACM/IEEE Design Automation Conference. Miami Beach, FL, USA, June 28, 1987

1986

Performance Measurement of Paging Behavior in Multiprogramming Systems.

Mohammad Malkawi, Janak H. Patel

Proceedings of the 13th Annual Symposium on Computer Architecture, Tokyo, Japan, June 1986, 1986

Effectiveness of heuristics measures for automatic test pattern generation.

Sanjay J. Patel, Janak H. Patel

Proceedings of the 23rd ACM/IEEE Design Automation Conference. Las Vegas, 1986

1985

Compiler Directed Memory Management Policy For Numerical Programs.

Mohammad Malkawi, Janak H. Patel

Proceedings of the Tenth ACM Symposium on Operating System Principles, 1985

Multiple-Fault Detection in Iterative Logic Arrays.

Wu-Tung Cheng, Janak H. Patel

Proceedings of the Proceedings International Test Conference 1985, 1985

An Efficient LISP-Execution Architecture with a New Representation for List Structures.

Gurindar S. Sohi, Edward S. Davidson, Janak H. Patel

Proceedings of the 12th Annual Symposium on Computer Architecture, 1985

Parallel Garbage Collection Without Synchronization Overhead.

Ashwin Ram, Janak H. Patel

Proceedings of the 12th Annual Symposium on Computer Architecture, 1985

1984

Design of Test Pattern Generators for Built-In Test.

Ramaswami Dandapani, Janak H. Patel, Jacob A. Abraham

Proceedings of the Proceedings International Test Conference 1984, 1984

A Low-Overhead Coherence Solution for Multiprocessors with Private Cache Memories.

Mark S. Papamarcos, Janak H. Patel

Proceedings of the 11th Annual Symposium on Computer Architecture, 1984

1983

Shared Cache for Multiple-Stream Computer Systems.

Phil C. C. Yeh, Janak H. Patel, Edward S. Davidson

IEEE Trans. Computers, 1983

Concurrent Error Detection in Multiply and Divide Arrays.

Janak H. Patel, Leona Y. Fung

IEEE Trans. Computers, 1983

Performance of Shared Cache for Parallel-Pipelined Computer Systems

Phil C. C. Yeh, Janak H. Patel, Edward S. Davidson

Proceedings of the 10th Annual Symposium on Computer Architecture, 1983, 1983

1982

Memory Interference in Synchronous Multiprocessor Systems.

David W. L. Yen, Janak H. Patel, Edward S. Davidson

IEEE Trans. Computers, 1982

Concurrent Error Detection in ALU's by Recomputing with Shifted Operands.

Janak H. Patel, Leona Y. Fung

IEEE Trans. Computers, 1982

Analysis of Multiprocessors with Private Cache Memories.

Janak H. Patel

IEEE Trans. Computers, 1982

A performance model for instruction prefetch in pipelined instruction units.

Gregory F. Grohoski, Janak H. Patel

Proceedings of the International Conference on Parallel Processing, 1982

1981

Performance of Processor-Memory Interconnections for Multiprocessors.

Janak H. Patel

IEEE Trans. Computers, 1981

1980

An Alternative to the Distributed Pipeline.

Janak H. Patel

IEEE Trans. Computers, 1980

1979

PM⁴ - A reconfigurable multiprocessor system for pattern recognition and image processing.

Faye A. Briggs, King-Sun Fu, Kai Hwang, Janak H. Patel

Proceedings of the 1979 International Workshop on Managing Requirements Knowledge, 1979

Processor-Memory Interconnections for Multiprocessors.

Janak H. Patel

Proceedings of the 6th Annual Symposium on Computer Architecture, 1979

1978

Pipelines wth Internal Buffers.

Janak H. Patel

Proceedings of the 5th Annual Symposium on Computer Architecture, 1978

1976

Improving the Throughput of a Pipeline by Insertion of Delays.

Janak H. Patel, Edward S. Davidson

Proceedings of the 3rd Annual Symposium on Computer Architecture, 1976