Jan Weinstock

Orcid: 0009-0008-0902-7652

According to our database1, Jan Weinstock authored at least 21 papers between 2007 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2024
Towards High-Performance Virtual Platforms: A Parallelization Strategy for SystemC TLM-2.0 CPU Models.
Proceedings of the 61st ACM/IEEE Design Automation Conference, 2024

2023
Efficient RISC-V-on-x64 Floating Point Simulation.
Proceedings of the 41st IEEE International Conference on Computer Design, 2023

Work-in-Progress: A Generic Non-Intrusive Parallelization Approach for SystemC TlM-2.0-Based Virtual Platforms.
Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis, 2023

2019
Fast SystemC Processor Models with Unicorn.
Proceedings of the Rapid Simulation and Performance Evaluation: Methods and Tools, 2019

2018
Fully Virtual Rapid ADAS Prototyping via a Joined Multi-domain Co-simulation Ecosystem.
Proceedings of the 4th International Conference on Vehicle Technology and Intelligent Transport Systems, 2018

A Multi-domain Co-simulation Ecosystem for Fully Virtual Rapid ADAS Prototyping.
Proceedings of the Smart Cities, Green Technologies and Intelligent Transport Systems, 2018

AMVP - a high performance virtual platform using parallel systemC for multicore ARM architectures: work-in-progress.
Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis, 2018

2017
Accelerating MPSoC Simulation Using Parallel SystemC and Processor Sleep Models.
Proceedings of the 9th Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools, 2017

2016
Parallel SystemC Simulation for ESL Design.
ACM Trans. Embed. Comput. Syst., 2016

SystemC-link: Parallel SystemC simulation using time-decoupled segments.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

Low-Cost Hardware Infrastructure for Runtime Thread Level Energy Accounting.
Proceedings of the Architecture of Computing Systems - ARCS 2016, 2016

2015
Modeling Exclusive Memory Access for a Time-Decoupled Parallel SystemC Simulator.
Proceedings of the 18th International Workshop on Software and Compilers for Embedded Systems, 2015

Parallel SystemC simulation for ESL design using flexible time decoupling.
Proceedings of the 2015 International Conference on Embedded Computer Systems: Architectures, 2015

Direct FPGA-based power profiling for a RISC processor.
Proceedings of the 2015 IEEE International Instrumentation and Measurement Technology Conference (I2MTC) Proceedings, 2015

2014
legaSCi: Legacy SystemC Model Integration into Parallel Simulators.
ACM Trans. Embed. Comput. Syst., 2014

EURETILE Design Flow: Dynamic and Fault Tolerant Mapping of Multiple Applications Onto Many-Tile Systems.
Proceedings of the IEEE International Symposium on Parallel and Distributed Processing with Applications, 2014

Time-decoupled parallel SystemC simulation.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

2013
legaSCi: Legacy SystemC Model Integration into Parallel Systemc Simulators.
Proceedings of the 2013 IEEE International Symposium on Parallel & Distributed Processing, 2013

2012
Cause and effect of nondeterministic behavior in sequential and parallel SystemC simulators.
Proceedings of the 2012 IEEE International High Level Design Validation and Test Workshop, 2012

SCandal: SystemC Analysis for Nondeterminism Anomalies.
Proceedings of the Models, Methods, and Tools for Complex Chip Design, 2012

2007
HySim: a fast simulation framework for embedded software development.
Proceedings of the 5th International Conference on Hardware/Software Codesign and System Synthesis, 2007


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