Jan van Lunteren

According to our database1, Jan van Lunteren authored at least 24 papers between 2001 and 2023.

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Bibliography

2023
Acceleration of Decision-Tree Ensemble Models on the IBM Telum Processor.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023

Accelerating Decision-Tree-Based Inference Through Adaptive Parallelization.
Proceedings of the 32nd International Conference on Parallel Architectures and Compilation Techniques, 2023

2019
Coherently Attached Programmable Near-Memory Acceleration Platform and its application to Stencil Processing.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

2018
Near-Memory Acceleration for Radio Astronomy.
IEEE Trans. Parallel Distributed Syst., 2018

2017
An Architecture for Integrated Near-Data Processors.
ACM Trans. Archit. Code Optim., 2017

Contutto: a novel FPGA-based prototyping platform enabling innovation in the memory subsystem of a server class processor.
Proceedings of the 50th Annual IEEE/ACM International Symposium on Microarchitecture, 2017

2016
Exploring the Design Space of an Energy-Efficient Accelerator for the SKA1-Low Central Signal Processor.
Int. J. Parallel Program., 2016

Scalable DFA Compilation for High-Performance Regular-Expression Matching.
Proceedings of the 19th International Workshop on Software and Compilers for Embedded Systems, 2016

An architecture for near-data processing systems.
Proceedings of the ACM International Conference on Computing Frontiers, CF'16, 2016

2015
Memristor based computation-in-memory architecture for data-intensive applications.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

An energy-efficient custom architecture for the SKA1-low central signal processor.
Proceedings of the 12th ACM International Conference on Computing Frontiers, 2015

2014
Scalable, efficient ASICS for the square kilometre array: From A/D conversion to central correlation.
Proceedings of the IEEE International Conference on Acoustics, 2014

2013
Wire-Speed Regular-Expression Scanning at 20 Gbit/s and Beyond.
ERCIM News, 2013

Hardware-Accelerated Regular Expression Matching with Overlap Handling on IBM PowerEN Processor.
Proceedings of the 27th IEEE International Symposium on Parallel and Distributed Processing, 2013

2012
Designing a Programmable Wire-Speed Regular-Expression Matching Accelerator.
Proceedings of the 45th Annual IEEE/ACM International Symposium on Microarchitecture, 2012

Hardware-accelerated regular expression matching at multiple tens of Gb/s.
Proceedings of the IEEE INFOCOM 2012, Orlando, FL, USA, March 25-30, 2012, 2012

2009
Memory-efficient distribution of regular expressions for fast deep packet inspection.
Proceedings of the 7th International Conference on Hardware/Software Codesign and System Synthesis, 2009

2006
High-Performance Pattern-Matching for Intrusion Detection.
Proceedings of the INFOCOM 2006. 25th IEEE International Conference on Computer Communications, 2006

A novel processor architecture for high-performance stream processing.
Proceedings of the 2006 IEEE Hot Chips 18 Symposium (HCS), 2006

2003
Fast and scalable packet classification.
IEEE J. Sel. Areas Commun., 2003

Design methodology for a modular service-driven network processor architecture.
Comput. Networks, 2003

2002
Dynamic multi-field packet classification.
Proceedings of the Global Telecommunications Conference, 2002

2001
Searching very large routing tables in fast SRAM.
Proceedings of the 10th International Conference on Computer Communications and Networks, 2001

Searching very large routing tables in wide embedded memory.
Proceedings of the Global Telecommunications Conference, 2001


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