Jan Schat

According to our database, Jan Schat authored at least 12 papers between 2006 and 2019.

Collaborative distances:

• Dijkstra number of six.
• Erdős number of six.

2019

Concurrent Estimation of a PLL Transfer Function by Cross-Correlation with pseudo-random Jitter.

Jan Schat, Ulrich Möhlmann

Proceedings of the 24th IEEE European Test Symposium, 2019

2018

ADC test methods using an impure stimulus: A survey.

Jan Schat

Proceedings of the 23rd IEEE European Test Symposium, 2018

On-line RF built-in self-test using noise injection and transmitter signal modulation by phase shifter.

Jan Schat

Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

2017

ISO26262-compliant soft-error mitigation in register banks.

Jan Schat

Proceedings of the 22nd IEEE European Test Symposium, 2017

Soft-error detection in Register Files using circular scan.

Jan Schat

Proceedings of the 12th International Conference on Design & Technology of Integrated Systems In Nanoscale Era, 2017

2009

Core-Based Testing of Embedded Mixed-Signal Modules in a SoC.

Vladimir A. Zivkovic, Jan Schat, Frank van der Heyden, Geert Seuren

IEEE Des. Test Comput., 2009

On the relationship between stuck-at fault coverage and transition fault coverage.

Jan Schat

Proceedings of the Design, Automation and Test in Europe, 2009

2008

Evaluation of the Iddq Signature in devices with Gauss-distributed background current.

Jan Schat

Proceedings of the 11th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2008), 2008

Calculating the fault coverage for dual neighboring faults using single stuck-at fault patterns.

Jan Schat

Proceedings of the 11th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2008), 2008

Fault Clustering in deep-submicron CMOS Processes.

Jan Schat

Proceedings of the Design, Automation and Test in Europe, 2008

2007

Testing low-resolution DACs using the Generalized Morse Sequence as Stimulus Sequence for Cancelling DC drift.

Jan Schat

Proceedings of the 14th IEEE International Conference on Electronics, 2007

2006

Simulation of SoCs with embedded mixed-signal Cores using a Verilog High-Speed Virtual Serial Interface.

Jan Schat

Proceedings of the 13th IEEE International Conference on Electronics, 2006