Jan Lappas
According to our database1,
Jan Lappas
authored at least 14 papers
between 2019 and 2024.
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2024
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Bibliography
2024
Proceedings of the 32nd IFIP/IEEE International Conference on Very Large Scale Integration, 2024
Proceedings of the 2024 IEEE Nordic Circuits and Systems Conference (NorCAS), 2024
Proceedings of the 22nd IEEE Interregional NEWCAS Conference, 2024
Proceedings of the 21st International SoC Design Conference, 2024
Proceedings of the 29th Asia and South Pacific Design Automation Conference, 2024
2022
A Weighted Current Summation Based Mixed Signal DRAM-PIM Architecture for Deep Neural Network Inference.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2022
Proceedings of the 29th IEEE International Conference on Electronics, Circuits and Systems, 2022
Machine learning based soft error rate estimation of pass transistor logic in high-speed communication.
Proceedings of the IEEE European Test Symposium, 2022
Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022
2021
J. Signal Process. Syst., 2021
A Novel DRAM Architecture for Improved Bandwidth Utilization and Latency Reduction Using Dual-Page Operation.
IEEE Trans. Circuits Syst. II Express Briefs, 2021
2020
J. Signal Process. Syst., 2020
2019
Proceedings of the Embedded Computer Systems: Architectures, Modeling, and Simulation, 2019
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019