Jan Kastil

According to our database, Jan Kastil authored at least 17 papers between 2009 and 2016.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2016

Optimalizace algoritmů a DatovýCH Struktur Pro VyhledáVání ReguláRníCH VýRazů S VyužITíM Technologie FPGA ; Optimization of Algorithms and Data Structures for Regular expression Matching using FPGA Technology.

Jan Kastil

PhD thesis, 2016

2015

Fault tolerant Field Programmable Neural Networks.

Martin Krcma, Zdenek Kotásek, Jan Kastil

Proceedings of the Nordic Circuits and Systems Conference, 2015

Mapping Trained Neural Networks to FPNNs.

Martin Krcma, Jan Kastil, Zdenek Kotásek

Proceedings of the 18th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2015

2014

Automatic Construction of On-line Checking Circuits Based on Finite Automata.

Lucie Matuova, Jan Kastil, Zdenek Kotásek

Proceedings of the 17th Euromicro Conference on Digital System Design, 2014

2013

Fault tolerant system design and SEU injection based testing.

Martin Straka, Jan Kastil, Zdenek Kotásek, Lukas Miculka

Microprocess. Microsystems, 2013

Fault tolerant CAN bus control system implemented into FPGA.

Karel Szurman, Jan Kastil, Martin Straka, Zdenek Kotásek

Proceedings of the 16th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2013

Hardware architecture for the fast pattern matching.

Jan Kastil, Vlastimil Kosar, Jan Korenek

Proceedings of the 16th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2013

2012

Dependability Analysis of Fault Tolerant Systems Based on Partial Dynamic Reconfiguration Implemented into FPGA.

Jan Kastil, Martin Straka, Lukas Miculka, Zdenek Kotásek

Proceedings of the 15th Euromicro Conference on Digital System Design, 2012

Test platform for fault tolerant systems design properties verification.

Martin Straka, Lukas Miculka, Jan Kastil, Zdenek Kotásek

Proceedings of the IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2012

2011

SEU Simulation Framework for Xilinx FPGA: First Step towards Testing Fault Tolerant Systems.

Martin Straka, Jan Kastil, Zdenek Kotásek

Proceedings of the 14th Euromicro Conference on Digital System Design, 2011

Advanced fault tolerant bus for multicore system implemented in FPGA.

Martin Straka, Jan Kastil, Jaroslav Novotný, Zdenek Kotásek

Proceedings of the 14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2011

Netbench: Framework for Evaluation of Packet Processing Algorithms.

Viktor Pus, Jiri Tobola, Vlastimil Kosar, Jan Kastil, Jan Korenek

Proceedings of the 2011 ACM/IEEE Symposium on Architectures for Networking and Communications Systems (ANCS), 2011

2010

Fault Tolerant Structure for SRAM-Based FPGA via Partial Dynamic Reconfiguration.

Martin Straka, Jan Kastil, Zdenek Kotásek

Proceedings of the 13th Euromicro Conference on Digital System Design, 2010

Modern fault tolerant architectures based on partial dynamic reconfiguration in FPGAs.

Martin Straka, Jan Kastil, Zdenek Kotásek

Proceedings of the 13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2010

Hardware accelerated pattern matching based on Deterministic Finite Automata with perfect hashing.

Jan Kastil, Jan Korenek

Proceedings of the 13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2010

High speed pattern matching algorithm based on deterministic finite automata with faulty transition table.

Jan Kastil, Jan Korenek

Proceedings of the 2010 ACM/IEEE Symposium on Architecture for Networking and Communications Systems, 2010

2009

Methodology for Fast Pattern Matching by Deterministic Finite Automaton with Perfect Hashing.

Jan Kastil, Jan Korenek, Ondrej Lengál

Proceedings of the 12th Euromicro Conference on Digital System Design, 2009