Jan Butas

According to our database, Jan Butas authored at least 6 papers between 1999 and 2001.

Collaborative distances:

• Dijkstra number of six.
• Erdős number of four.

2001

A New Control Circuit for Asynchronous Micropipelines.

Oliver Chiu-sing Choy, Jan Butas, Juraj Povazanec, Cheong-Fat Chan

IEEE Trans. Computers, 2001

Asynchronous cross-pipelined multiplier.

Jan Butas, Chiu-Sing Choy, Juraj Povazanec, Cheong-Fat Chan

IEEE J. Solid State Circuits, 2001

A low power asynchronous DES.

Pui-Lam Siu, Chiu-sing Choy, Jan Butas, Cheong-Fat Chan

Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

A pipelined dataflow small micro-coded asynchronous processor and its application to DCT.

Chi-Wai Lee, Chiu-sing Choy, Jan Butas, Cheong-Fat Chan

Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

2000

An ALU design using a novel asynchronous pipeline architecture.

Tin-Yau Tang, Chiu-sing Choy, Jan Butas, Cheong-Fat Chan

Proceedings of the IEEE International Symposium on Circuits and Systems, 2000

1999

Pipelined Dataflow Architecture of a Small Processor.

Juraj Povazanec, Oliver Chiu-sing Choy, Cheong-Fat Chan, Jan Butas, Yeu-qiu Zhang, Jing-Ling Yang, Tin-yan Tang

Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, 1999