Jamie Liu

According to our database1, Jamie Liu authored at least 7 papers between 2012 and 2018.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2018
Tiered-Latency DRAM: Enabling Low-Latency Main Memory at Low Cost.
CoRR, 2018

Exploiting the DRAM Microarchitecture to Increase Memory-Level Parallelism.
CoRR, 2018

2016
Tiered-Latency DRAM (TL-DRAM).
CoRR, 2016

2013
An experimental study of data retention behavior in modern DRAM devices: implications for retention time profiling mechanisms.
Proceedings of the 40th Annual International Symposium on Computer Architecture, 2013

Tiered-latency DRAM: A low latency and low cost DRAM architecture.
Proceedings of the 19th IEEE International Symposium on High Performance Computer Architecture, 2013

2012
RAIDR: Retention-aware intelligent DRAM refresh.
Proceedings of the 39th International Symposium on Computer Architecture (ISCA 2012), 2012

A case for exploiting subarray-level parallelism (SALP) in DRAM.
Proceedings of the 39th International Symposium on Computer Architecture (ISCA 2012), 2012


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