James Read
Orcid: 0000-0003-2226-0340
According to our database1,
James Read
authored at least 12 papers
between 2007 and 2024.
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Bibliography
2024
Co-Optimization for Robust Power Delivery Design in 3D-Heterogeneous Integration of Compute In-Memory Accelerators.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits 2024, 2024
Engineering nvCap From FEOL to BEOL with Ferroelectric Small-signal Non-destructive Read.
Proceedings of the IEEE International Memory Workshop, 2024
A Cross-layer Framework for Design Space and Variation Analysis of Non-Volatile Ferroelectric Capacitor-Based Compute-in-Memory Accelerators.
Proceedings of the 29th Asia and South Pacific Design Automation Conference, 2024
2023
H3DAtten: Heterogeneous 3-D Integrated Hybrid Analog and Digital Compute-in-Memory Accelerator for Vision Transformer Self-Attention.
IEEE Trans. Very Large Scale Integr. Syst., October, 2023
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023
2022
MAC-ECC: In-Situ Error Correction and Its Design Methodology for Reliable NVM-Based Compute-in-Memory Inference Engine.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2022
A Method for Reverse Engineering Neural Network Parameters from Compute-in-Memory Accelerators.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2022
A 40nm RRAM Compute-in-Memory Macro with Parallelism-Preserving ECC for Iso-Accuracy Voltage Scaling.
Proceedings of the 48th IEEE European Solid State Circuits Conference, 2022
2021
2020
2013
LMS J. Comput. Math., 2013
2007
Proceedings of the 40th Hawaii International International Conference on Systems Science (HICSS-40 2007), 2007