James R. Armstrong

Affiliations:
  • Virginia Tech, Blacksburg, VA, USA


According to our database1, James R. Armstrong authored at least 27 papers between 1973 and 2004.

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Bibliography

2004
Synthesis of SystemC models from SDF Ptolemy descriptions.
Proceedings of the Proceedings 2004 IEEE International SOC Conference, 2004

2002
A Multi-Language Goal-Tree Based Functional Test Planning System.
Proceedings of the Proceedings IEEE International Test Conference 2002, 2002

1999
VHDL modeling and model testing for DSP applications.
IEEE Trans. Ind. Electron., 1999

1998
A goal tree based high-level test planning system for DSP real number models.
Proceedings of the Proceedings IEEE International Test Conference 1998, 1998

1996
Efficient approaches to testing VHDL DSP models.
J. VLSI Signal Process., 1996

1995
Efficient approaches to testing VHDL DSP models.
Proceedings of the 1995 International Conference on Acoustics, 1995

1994
B-algorithm: A Behavioral-Test Generation Algorithm.
Proceedings of the Proceedings IEEE International Test Conference 1994, 1994

1993
Hierarchical test generation: Where we are, and where we should be going.
Proceedings of the European Design Automation Conference 1993, 1993

The Modeler's Assistant: A CAD Tool for Behavioral Model Development.
Proceedings of the Computer Hardware Description Languages and their Applications, Proceedings of the 11th IFIP WG10.2 International Conference on Computer Hardware Description Languages and their Applications, 1993

1992
Timing distribution in VHDL behavioral models.
Proceedings of the 1992 IEEE/ACM International Conference on Computer-Aided Design, 1992

1990
Tuning VHDL for Multivalve Logic Modeling.
IEEE Des. Test Comput., 1990

Automated assists to the behavioral modeling process.
Proceedings of the First International Workshop on Rapid System Prototyping, 1990

Behavioral Fault Simulation in VHDL.
Proceedings of the 27th ACM/IEEE Design Automation Conference. Orlando, 1990

1989
t-TDA-Diagnosable Systems.
IEEE Trans. Computers, 1989

1986
A heuristic chip-level test generation algorithm.
Proceedings of the 23rd ACM/IEEE Design Automation Conference. Las Vegas, 1986

1985
Functional fault modeling and simulation for VLSI devices.
Proceedings of the 22nd ACM/IEEE conference on Design automation, 1985

1984
Chip Level Modeling of LSI Devices.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1984

1981
Tree Structured Sequential Multiple-Valued Logic Design from Universal Modules.
IEEE Trans. Computers, 1981

Representation of Multivalued Functions Using the Direct Cover Method.
IEEE Trans. Computers, 1981

Fault Diagnosos in a Boolean <i>n</i> Cube Array of Microprocessors.
IEEE Trans. Computers, 1981

GSP: A logic simulator for LSI.
Proceedings of the 18th Design Automation Conference, 1981

1980
The Complexity of Computational Circuits Versus Radix.
IEEE Trans. Computers, 1980

Special Feature Chip-Level Simulation of Microprocessors.
Computer, 1980

1978
A simultaneous, radix four, I2L multiplier mechanized via repeated addition.
Proceedings of the eighth international symposium on Multiple-valued logic, 1978

The modular complexity of a tree structured higher radix multiplier.
Proceedings of the eighth international symposium on Multiple-valued logic, 1978

1977
Simulation techniques for microprocessors.
Proceedings of the 14th Design Automation Conference, 1977

1973
Design of a Graphic Generator for Remote Terminal Application.
IEEE Trans. Computers, 1973


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