James Gorecki

According to our database, James Gorecki authored at least 3 papers between 2002 and 2017.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2017

A background calibrated 28GS/s 8b interleaved SAR ADC in 28nm CMOS.

Michael Q. Le, James Gorecki, Jamal Riani, Jorge Pernillo, A. Tan, K. Gopalakrishnan, Belal Helal, Pulkit Khandelwal, Chang-Feng Loi, Irene Quek, P. Wong, Aaron Buchwald

Proceedings of the 2017 IEEE Custom Integrated Circuits Conference, 2017

2016

3.4 A 40/50/100Gb/s PAM-4 Ethernet transceiver in 28nm CMOS.

Karthik Gopalakrishnan, Alan Ren, Amber Tan, Arash Farhood, Arun Tiruvur, Belal Helal, Chang-Feng Loi, Chris Jiang, Halil Cirit, Irene Quek, Jamal Riani, James Gorecki, Jennifer Wu, Jorge Pernillo, Lawrence Tse, Michael Q. Le, Mohammad Ranjbar, Pui-Shan Wong, Pulkit Khandelwal, Rajesh Narayanan, Ravindran Mohanavelu, Sameer Herlekar, Sudeep Bhoja, Vlad Shvydun

Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016

2002

An adaptive PAM-4 5 Gb/s backplane transceiver in 0.25 μm CMOS.

Jeff L. Sonntag, John T. Stonick, James Gorecki, Bill Beale, Bill Check, Xue-Mei Gong, Joe Guiliano, Kyong Lee, Bob Lefferts, David A. Yokoyama-Martin, Un-Ku Moon, Amber Sengir, Stephen Titus, Gu-Yeon Wei, Daniel Weinlader, YaoHua Yang

Proceedings of the IEEE 2002 Custom Integrated Circuits Conference, 2002