James E. Stine

Proceedings of the 67th IEEE International Midwest Symposium on Circuits and Systems, 2024

Power Reduction of Montgomery Multiplication Architectures Using Clock Gating.

[BibT_eX]

[DOI]

Rachana Erra

Proceedings of the 67th IEEE International Midwest Symposium on Circuits and Systems, 2024

Methodologies for Implementation of Standard-Cell Libraries for Radiation Hardened Environments.

[BibT_eX]

[DOI]

Ryan Ridley

George Suárez

Proceedings of the 15th IEEE Latin America Symposium on Circuits and Systems, 2024

2023

Evaluation of a Modular Approach to AES Hardware Architecture and Optimization.

[BibT_eX]

[DOI]

Pierre-Emmanuel Gaillardon

J. Signal Process. Syst., July, 2023

NSF Integrated Circuit Research, Education and Workforce Development Workshop Final Report.

[BibT_eX]

[DOI]

Matthew Guthaus

Christopher Batten

Erik Brunvand

CoRR, 2023

Design Exploration of Magnitude Comparators for RISC-V System-on-Chip Architectures.

[BibT_eX]

[DOI]

Alexander Underwood

Proceedings of the 57th Asilomar Conference on Signals, Systems, and Computers, ACSSC 2023, Pacific Grove, CA, USA, October 29, 2023

Parallelization of the Shift and Add Reducer.

[BibT_eX]

[DOI]

Proceedings of the 57th Asilomar Conference on Signals, Systems, and Computers, ACSSC 2023, Pacific Grove, CA, USA, October 29, 2023

2022

Implementation of High Performance IEEE 754-Posit Conversion Hardware.

[BibT_eX]

[DOI]

Brett Mathis

Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

Point-Targeted Sparseness and Ling Transforms on Parallel Prefix Adder Trees.

[BibT_eX]

[DOI]

Teodor-Dumitru Ene

Proceedings of the 29th IEEE Symposium on Computer Arithmetic, 2022

2021

A Comprehensive Exploration of the Parallel Prefix Adder Tree Space.

[BibT_eX]

[DOI]

Teodor-Dumitru Ene

Proceedings of the 39th IEEE International Conference on Computer Design, 2021

A Reconfigurable Architecture for Improvement and Optimization of Advanced Encryption Standard Hardware.

[BibT_eX]

[DOI]

Proceedings of the 55th Asilomar Conference on Signals, Systems, and Computers, 2021

2020

A Ling-Enhanced Adder for IEEE-compliant Floating-Point Multiplication.

[BibT_eX]

[DOI]

S. Ross Thompson

Proceedings of the 63rd IEEE International Midwest Symposium on Circuits and Systems, 2020

An Improved Hardware Architecture for modulo without Multiplication.

[BibT_eX]

[DOI]

Proceedings of the 63rd IEEE International Midwest Symposium on Circuits and Systems, 2020

An Efficient Implementation of Radix-4 Integer Division Using Scaling.

[BibT_eX]

[DOI]

Kevin Hill

Proceedings of the 63rd IEEE International Midwest Symposium on Circuits and Systems, 2020

A Novel Rounding Algorithm for a High Performance IEEE 754 Double-Precision Floating-Point Multiplier.

[BibT_eX]

[DOI]

S. Ross Thompson

Proceedings of the 38th IEEE International Conference on Computer Design, 2020

An Architecture for Improving Variable Radix Real and Complex Division Using Recurrence Division.

[BibT_eX]

[DOI]

Milos D. Ercegovac

Jean-Michel Muller

Proceedings of the 54th Asilomar Conference on Signals, Systems, and Computers, 2020

2019

An Emphasis on Memory and Processor Interactions in Undergraduate Computer Architecture Education.

[BibT_eX]

[DOI]

Alexander Underwood

Proceedings of the Workshop on Computer Architecture Education, 2019

Using Carry Increment Adders to Enhance Energy Savings with Spanning-Tree Adder Structures.

[BibT_eX]

[DOI]

Kyle Price

Proceedings of the 62nd IEEE International Midwest Symposium on Circuits and Systems, 2019

A Novel Single/Double Precision Normalized IEEE 754 Floating-Point Adder/Subtracter.

[BibT_eX]

[DOI]

Brett Mathis

Proceedings of the 2019 IEEE Computer Society Annual Symposium on VLSI, 2019

A Low-Power Recurrence-Based Radix 4 Divider Using Signed-Digit Addition.

[BibT_eX]

[DOI]

Matthew Gaalswyk

Proceedings of the 2019 IEEE Computer Society Annual Symposium on VLSI, 2019

Fast and Area-Efficient SRAM Word-Line Optimization.

[BibT_eX]

[DOI]

Bin Wu

Matthew R. Guthaus

Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

A Well-Equipped Implementation: Normal/Denormalized Half/Single/Double Precision IEEE 754 Floating-Point Adder/Subtracter.

[BibT_eX]

[DOI]

Brett Mathis

Proceedings of the 30th IEEE International Conference on Application-specific Systems, 2019

Conditional Estimation of Residuals with Prescaling for Use in Low-Energy Division Units.

[BibT_eX]

[DOI]

Milos D. Ercegovac

Proceedings of the 53rd Asilomar Conference on Signals, Systems, and Computers, 2019

2018

A 64 kB Approximate SRAM Architecture for Low-Power Video Applications.

[BibT_eX]

[DOI]

IEEE Embed. Syst. Lett., 2018

A Methodology for Low-Power Approximate Embedded SRAM Within Multimedia Applications.

[BibT_eX]

[DOI]

Proceedings of the 31st IEEE International System-on-Chip Conference, 2018

Clarifications and Optimizations on Rounding for IEEE-compliant Floating-Point Multiplication.

[BibT_eX]

[DOI]

Tuan D. Nguyen

Proceedings of the 29th IEEE International Conference on Application-specific Systems, 2018

Low-Area Memoryless optimized Soft-Decision Viterbi Decoder with Dedicated Paralell Squaring Architecture.

[BibT_eX]

[DOI]

John D. Tobola

Proceedings of the 52nd Asilomar Conference on Signals, Systems, and Computers, 2018

2017

Constant-based truncated cubing architectures.

[BibT_eX]

[DOI]

Proceedings of the IEEE 60th International Midwest Symposium on Circuits and Systems, 2017

A high performance multi-port SRAM for low voltage shared memory systems in 32 nm CMOS.

[BibT_eX]

[DOI]

Matthew Gaalswyk

Proceedings of the IEEE 60th International Midwest Symposium on Circuits and Systems, 2017

WIP. Open-source standard cell characterization process flow on 45 nm (FreePDK45), 0.18 µm, 0.25 µm, 0.35 µm and 0.5 µm.

[BibT_eX]

[DOI]

Rabin Thapa

Proceedings of the 2017 IEEE International Conference on Microelectronic Systems Education, 2017

Sustainable IC design and fabrication.

[BibT_eX]

[DOI]

Proceedings of the Eighth International Green and Sustainable Computing Conference, 2017

A Reconfigurable Replica Bitline to Determine Optimum SRAM Sense Amplifier Set Time.

[BibT_eX]

[DOI]

Proceedings of the on Great Lakes Symposium on VLSI 2017, 2017

A combined IEEE half and single precision floating point multipliers for deep learning.

[BibT_eX]

[DOI]

Tuan D. Nguyen

Proceedings of the 51st Asilomar Conference on Signals, Systems, and Computers, 2017

2016

A 64 kb differential single-port 12T SRAM design with a bit-interleaving scheme for low-voltage operation in 32 nm SOI CMOS.

[BibT_eX]

[DOI]

Matthew R. Guthaus

Proceedings of the 34th IEEE International Conference on Computer Design, 2016

OpenRAM: an open-source memory compiler.

[BibT_eX]

[DOI]

Proceedings of the 35th International Conference on Computer-Aided Design, 2016

Optimized multipartite table methods for elementary function computation.

[BibT_eX]

[DOI]

Proceedings of the 50th Asilomar Conference on Signals, Systems and Computers, 2016

2015

Revisiting redundant Booth with bias multipliers.

[BibT_eX]

[DOI]

Sampoorna Mallipeddi

Proceedings of the IEEE 58th International Midwest Symposium on Circuits and Systems, 2015

A differential single-port 8T SRAM bitcell for variability tolerance and low voltage operation.

[BibT_eX]

[DOI]

Proceedings of the Sixth International Green and Sustainable Computing Conference, 2015

Multi Replica Bitline Delay Technique for Variation Tolerant Timing of SRAM Sense Amplifiers.

[BibT_eX]

[DOI]

Proceedings of the 25th edition on Great Lakes Symposium on VLSI, GLVLSI 2015, Pittsburgh, PA, USA, May 20, 2015

An IEEE 754 double-precision floating-point multiplier for denormalized and normalized floating-point numbers.

[BibT_eX]

[DOI]

S. Ross Thompson

Proceedings of the 26th IEEE International Conference on Application-specific Systems, 2015

2014

Experiments with High Speed Parallel Cubing Units.

[BibT_eX]

[DOI]

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2014

Enhancing the Unified Logical Effort algorithm for branching and load distribution.

[BibT_eX]

[DOI]

Mehedi Sarwar

Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

Optimized cubic chebyshev interpolator for elementary function hardware implementations.

[BibT_eX]

[DOI]

E. George Walters III

Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

Additional optimizations for parallel squarer units.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

2012

Elementary function approximation using optimized most significant bits of Chebyshev coefficients and truncated multipliers.

[BibT_eX]

[DOI]

Proceedings of the 55th IEEE International Midwest Symposium on Circuits and Systems, 2012

Session TA6b: Low power II (invited).

[BibT_eX]

[DOI]

Proceedings of the Conference Record of the Forty Sixth Asilomar Conference on Signals, 2012

Optimized low-power elementary function approximation for Chebyshev series approximations.

[BibT_eX]

[DOI]

Proceedings of the Conference Record of the Forty Sixth Asilomar Conference on Signals, 2012

2011

A recursive-divide architecture for multiplication and division.

[BibT_eX]

[DOI]

Amey Phadke

Surpriya Tike

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

2009

FreePDK v2.0: Transitioning VLSI education towards nanometer variation-aware designs.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference on Microelectronic Systems Education, 2009

Parallel Prefix Ling Structures for Modulo 2^n-1 Addition.

[BibT_eX]

[DOI]

Jun Chen

Proceedings of the 20th IEEE International Conference on Application-Specific Systems, 2009

2008

Compressor trees for decimal partial product reduction.

[BibT_eX]

[DOI]

Ivan D. Castellanos

Proceedings of the 18th ACM Great Lakes Symposium on VLSI 2008, 2008

Session WA5b: Low power methods.

[BibT_eX]

[DOI]

Proceedings of the 42nd Asilomar Conference on Signals, Systems and Computers, 2008

Single-ended half-swing low-power SRAM design.

[BibT_eX]

[DOI]

Harsha Choday

Proceedings of the 42nd Asilomar Conference on Signals, Systems and Computers, 2008

2007

FreePDK: An Open-Source Variation-Aware Design Kit.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference on Microelectronic Systems Education, 2007

Partial Product Reduction for Parallel Cubing.

[BibT_eX]

[DOI]

Jeff M. Blank

Proceedings of the 2007 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2007), 2007

2006

Dual-Mode High-Speed Low-Energy Binary Addition.

[BibT_eX]

[DOI]

Proceedings of the 2006 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2006), 2006

Compressed symmetric tables for accurate function approximation of reciprocals.

[BibT_eX]

[DOI]

Nitin Naresh

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

Low power binary addition using carry increment adders.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

A 64-bit Decimal Floating-Point Comparator.

[BibT_eX]

[DOI]

Ivan D. Castellanos

Proceedings of the 2006 IEEE International Conference on Application-Specific Systems, 2006

2005

A Framework for High-Level Synthesis of System-on-Chip Designs.

[BibT_eX]

[DOI]

Proceedings of the 2005 International Conference on Microelectronics Systems Education, 2005

Real World SOC Experience for the Classroom.

[BibT_eX]

[DOI]

David D. Neiman

Proceedings of the 2005 International Conference on Microelectronics Systems Education, 2005

A combined two's complement and floating-point comparator.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Constant addition utilizing flagged prefix structures.

[BibT_eX]

[DOI]

Christopher R. Babb

Vibhuti B. Dave

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

New algorithms for carry propagation.

[BibT_eX]

[DOI]

Proceedings of the 15th ACM Great Lakes Symposium on VLSI 2005, 2005

2004

Intrinsic Compiler Support for Interval Arithmetic.

[BibT_eX]

[DOI]

Ahmet Akkas

Numer. Algorithms, 2004

Parallel Programmable Finite Field GF(2m) Multipliers.

[BibT_eX]

[DOI]

Nick Iliev

Nathan Jachimiec

Proceedings of the 2004 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2004), 2004

Modified booth truncated multipliers.

[BibT_eX]

[DOI]

Alok A. Katkar

Proceedings of the 14th ACM Great Lakes Symposium on VLSI 2004, 2004

2003

A Standard Cell Library for Student Projects.

[BibT_eX]

[DOI]

Proceedings of the 2003 International Conference on Microelectronics Systems Education, 2003

A pipelined clock-delayed domino carry-lookahead adder.

[BibT_eX]

[DOI]

Bhushan A. Shinkre

Proceedings of the 13th ACM Great Lakes Symposium on VLSI 2003, 2003

Variations on Truncated Multiplication.

[BibT_eX]

[DOI]

Oliver M. Duverne

Proceedings of the 2003 Euromicro Symposium on Digital Systems Design (DSD 2003), 2003

2001

Combined IEEE Compliant and Truncated Floating Point Multipliers for Reduced Power Dissipation.

[BibT_eX]

[DOI]

Kent E. Wires

Proceedings of the 19th International Conference on Computer Design (ICCD 2001), 2001

1999

The Symmetric Table Addition Method for Accurate Function Approximation.

[BibT_eX]

[DOI]

J. VLSI Signal Process., 1999

Approximating Elementary Functions with Symmetric Bipartite Tables.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 1999

1998

A Combined Interval and Floating Point Multiplier.

[BibT_eX]

[DOI]

Proceedings of the 8th Great Lakes Symposium on VLSI (GLS-VLSI '98), 1998

1997

Accurate Function Approximations by Symmetric Table Lookup and Addition.

[BibT_eX]

[DOI]

Proceedings of the 1997 International Conference on Application-Specific Systems, 1997

Symmetric Bipartite Tables for Accurate Function Approximation.

[BibT_eX]

[DOI]