James D. Meindl

IEEE Trans. Very Large Scale Integr. Syst., 2008

Physical models for electron transport in graphene nanoribbons and their junctions.

[BibT_eX]

[DOI]

Azad Naeemi

Proceedings of the 2008 International Conference on Computer-Aided Design, 2008

3D heterogeneous integrated systems: Liquid cooling, power delivery, and implementation.

[BibT_eX]

[DOI]

Proceedings of the IEEE 2008 Custom Integrated Circuits Conference, 2008

2007

Carbon nanotube interconnects.

[BibT_eX]

[DOI]

Azad Naeemi

Proceedings of the 2007 International Symposium on Physical Design, 2007

IntSim: A CAD tool for optimization of multilevel interconnect networks.

[BibT_eX]

[DOI]

Proceedings of the 2007 International Conference on Computer-Aided Design, 2007

Performance Modeling and Optimization for Single- and Multi-Wall Carbon Nanotube Interconnects.

[BibT_eX]

[DOI]

Azad Naeemi

Reza Sarvari

Proceedings of the 44th Design Automation Conference, 2007

Physical Model for Power Supply Noise and Chip/Package Co-Design in Gigascale Systems with the Consideration of Hot Spots.

[BibT_eX]

[DOI]

Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, 2007

Revolutionary NanoSilicon Ancillary Technologies for Ultimate-Performance Gigascale Systems.

[BibT_eX]

[DOI]

Muhannad S. Bakir

Bing Dang

Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, 2007

2006

Prospects for Wafer-Level Testing of Gigascale Chips with Electrical and Optical I/O Interconnects.

[BibT_eX]

[DOI]

Hiren D. Thacker

Proceedings of the 2006 IEEE International Test Conference, 2006

2004

Global interconnect design in a three-dimensional system-on-a-chip.

[BibT_eX]

[DOI]

James W. Joyner

Payman Zarkesh-Ha

IEEE Trans. Very Large Scale Integr. Syst., 2004

Coaxial polymer pillars: ultra-low inductance compliant wafer-level electrical input/output interconnects for power distribution.

[BibT_eX]

[DOI]

Muhannad S. Bakir

Proceedings of the Proceedings 2004 IEEE International SOC Conference, 2004

Relative inductance extraction method.

[BibT_eX]

[DOI]

Proceedings of the IEEE 2004 Custom Integrated Circuits Conference, 2004

2003

Modeling technology impact on cluster microprocessor performance.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2003

Interconnect Opportunities for Gigascale Integration.

[BibT_eX]

[DOI]

IEEE Micro, 2003

Beyond Moore's Law: the interconnect era.

[BibT_eX]

[DOI]

Comput. Sci. Eng., 2003

2002

Electrical and optical clock distribution networks for gigascale microprocessors.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2002

Impact of die-to-die and within-die parameter fluctuations on the maximum clock frequency distribution for gigascale integration.

[BibT_eX]

[DOI]

Keith A. Bowman

Steven G. Duvall

IEEE J. Solid State Circuits, 2002

Interconnect opportunities for gigascale integration.

[BibT_eX]

[DOI]

IBM J. Res. Dev., 2002

Temperature Variable Supply Voltage for Power Reduction.

[BibT_eX]

[DOI]

Proceedings of the 2002 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2002), 2002

Low-power circuit advantages of the scaled accumulation FET.

[BibT_eX]

[DOI]

Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

A compact delay model for series-connected MOSFETs.

[BibT_eX]

[DOI]

Proceedings of the 12th ACM Great Lakes Symposium on VLSI 2002, 2002

A physical model for the transient response of capacitively loaded distributed rlc interconnects.

[BibT_eX]

[DOI]

Raguraman Venkatesan

Jeffrey A. Davis

Proceedings of the 39th Design Automation Conference, 2002

Sea of leads (SoL) characterization and design for compatibility with board-level optical waveguide interconnection.

[BibT_eX]

[DOI]

Proceedings of the IEEE 2002 Custom Integrated Circuits Conference, 2002

2001

Optimal n-tier multilevel interconnect architectures for gigascale integration (GSI).

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2001

Impact of three-dimensional architectures on interconnects in gigascale integration.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2001

Architecture of the Atlas Chip-Multiprocessor: Dynamically Parallelizing Irregular Applications.

[BibT_eX]

[DOI]

Lucian Codrescu

D. Scott Wills

IEEE Trans. Computers, 2001

Special issue on limits of semiconductor technology.

[BibT_eX]

[DOI]

Proc. IEEE, 2001

Interconnect limits on gigascale integration (GSI) in the 21st century.

[BibT_eX]

[DOI]

Proc. IEEE, 2001

The impact of intrinsic device fluctuations on CMOS SRAM cell stability.

[BibT_eX]

[DOI]

Xinghai Tang

IEEE J. Solid State Circuits, 2001

On The Micro-architectural Impact of Clock Distribution Using Multiple PLLs.

[BibT_eX]

[DOI]

Martin Saint-Laurent

Madhavan Swaminathan

Proceedings of the 19th International Conference on Computer Design (ICCD 2001), 2001

Interconnect-centric Array Architectures for Minimum SRAM Access Time.

[BibT_eX]

[DOI]

Stephen V. Kosonocky

Proceedings of the 19th International Conference on Computer Design (ICCD 2001), 2001

Impact of within-die parameter fluctuations on future maximum clock frequency distributions.

[BibT_eX]

[DOI]

Keith A. Bowman

Proceedings of the IEEE 2001 Custom Integrated Circuits Conference, 2001

2000

Prediction of net-length distribution for global interconnects in a heterogeneous system-on-a-chip.

[BibT_eX]

[DOI]

Payman Zarkesh-Ha

Jeffrey A. Davis

IEEE Trans. Very Large Scale Integr. Syst., 2000

A compact physical via blockage model.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2000

Heterogeneous architecture models for interconnect-motivated system design.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2000

A minimum total power methodology for projecting limits on CMOS GSI.

[BibT_eX]

[DOI]

Keith A. Bowman

IEEE Trans. Very Large Scale Integr. Syst., 2000

The fundamental limit on binary switching energy for terascale integration (TSI).

[BibT_eX]

[DOI]

Jeffrey A. Davis

IEEE J. Solid State Circuits, 2000

Prediction of interconnect fan-out distribution using Rent's rule.

[BibT_eX]

[DOI]

Proceedings of the Second IEEE/ACM International Workshop on System-Level Interconnect Prediction (SLIP 2000), 2000

Vertical pitch limitations on performance enhancement in bonded three-dimensional interconnect architectures.

[BibT_eX]

[DOI]

Proceedings of the Second IEEE/ACM International Workshop on System-Level Interconnect Prediction (SLIP 2000), 2000

Gigascale integration (GSI) interconnect limits and n-tier multilevel interconnect architectural solutions (discussion session).

[BibT_eX]

[DOI]

Proceedings of the Second IEEE/ACM International Workshop on System-Level Interconnect Prediction (SLIP 2000), 2000

Minimum power and area n-tier multilevel interconnect architectures using optimal repeater insertion.

[BibT_eX]

[DOI]

Proceedings of the 2000 International Symposium on Low Power Electronics and Design, 2000

CMOS system-on-a-chip voltage scaling beyond 50nm.

[BibT_eX]

[DOI]

Ashok Kapoor

Proceedings of the 10th ACM Great Lakes Symposium on VLSI 2000, 2000

1999

A physical alpha-power law MOSFET model.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 1999

Characterization and modeling of clock skew with process variations.

[BibT_eX]

[DOI]

Payman Zarkesh-Ha

Tony Mule

Proceedings of the IEEE 1999 Custom Integrated Circuits Conference, 1999

XXI Century Gigascale Integration (GSI) : The Interconnect Problem.

[BibT_eX]

[DOI]

Proceedings of the 18th Conference on Advanced Research in VLSI (ARVLSI '99), 1999

Exploring Microprocessor Architectures for Gigascale Integration.

[BibT_eX]

[DOI]

Proceedings of the 18th Conference on Advanced Research in VLSI (ARVLSI '99), 1999

1998

Minimum supply voltage for bulk Si CMOS GSI.

[BibT_eX]

[DOI]

Proceedings of the 1998 International Symposium on Low Power Electronics and Design, 1998

On a pin versus gate relationship for heterogeneous systems: heterogeneous Rent's rule.

[BibT_eX]

[DOI]

Proceedings of the IEEE 1998 Custom Integrated Circuits Conference, 1998

1997

Intrinsic MOSFET parameter fluctuations due to random dopant placement.

[BibT_eX]

[DOI]

Xinghai Tang

IEEE Trans. Very Large Scale Integr. Syst., 1997

A history of low power electronics: how it began and where it's headed.

[BibT_eX]

[DOI]

Proceedings of the 1997 International Symposium on Low Power Electronics and Design, 1997

1996

Effects of random MOSFET parameter fluctuations on total power consumption.

[BibT_eX]

[DOI]

Xinghai Tang

Proceedings of the 1996 International Symposium on Low Power Electronics and Design, 1996

A dynamic energy recycling logic family for ultra-low-power gigascale integration (GSI).

[BibT_eX]

[DOI]

Proceedings of the 1996 International Symposium on Low Power Electronics and Design, 1996

Circuit techniques for low-power CMOS GSI.

[BibT_eX]

[DOI]

Proceedings of the 1996 International Symposium on Low Power Electronics and Design, 1996

1995

Low power microelectronics: retrospect and prospect.

[BibT_eX]

[DOI]

Proc. IEEE, 1995

1994

Short channel models and scaling limits of SOI and bulk MOSFETs.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, February, 1994

1991

Gigascale integration (GSI) technology.

[BibT_eX]

[DOI]

Proceedings of the Proceedings Supercomputing '91, 1991

Design and Test Automation-Gigascale Integration (GSI) in the 21st Century.

[BibT_eX]

[DOI]

Proceedings of the Proceedings 1991 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1991

1988

Offset word-line architecture for scaling DRAMs to the gigabit level.

[BibT_eX]

[DOI]

Roy E. Scheuerlein

IEEE J. Solid State Circuits, February, 1988

1986

Scanning the issue.

[BibT_eX]

[DOI]

Kenneth A. Pickar