Jalil Kamali

According to our database1, Jalil Kamali authored at least 8 papers between 2005 and 2021.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2021
Baud rate pattern-adaptable dual loop clock recovery for high speed serial links.
Proceedings of the 55th Asilomar Conference on Signals, Systems, and Computers, 2021

2020
UBC2019 - A dataset of subjective image quality of head-mounted displays.
Dataset, March, 2020

2019
Symbol spaced clock recovery for high speed links.
Proceedings of the 13th International Conference on Signal Processing and Communication Systems, 2019

A 1.5pJ/bit, 5-to-10Gbps Forwarded-Clock I/O with Per-Lane Clock De-Skew in a Low Power 28nm CMOS Process.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2019

2016
23.3 A 6Gb/s 3-tap FFE transmitter and 5-tap DFE receiver in 65nm/0.18µm CMOS for next-generation 8K displays.
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016

2015
BER analysis of high speed links with nonlinearity.
Proceedings of the 49th Asilomar Conference on Signals, Systems and Computers, 2015

2012
Design of high-speed wireline transceivers for backplane communications in 28nm CMOS.
Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, 2012

2005
Competition stimulates technology advances: experiences from ADSL development in Japan.
IEEE Commun. Mag., 2005


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