Jakub Kedzierski

According to our database, Jakub Kedzierski authored at least 4 papers between 2002 and 2010.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2010

FDSOI Process Technology for Subthreshold-Operation Ultralow-Power Electronics.

Steven A. Vitale, Peter W. Wyatt, Nisha Checka, Jakub Kedzierski, Craig L. Keast

Proc. IEEE, 2010

2003

Scaling beyond the 65 nm node with FinFET-DGCMOS.

Edward J. Nowak, Thomas Ludwig, Ingo Aller, Jakub Kedzierski, M. Leong, BethAnn Rainey, Matthew J. Breitwisch, V. Gemhoefer, Joachim Keinert, David M. Fried

Proceedings of the IEEE Custom Integrated Circuits Conference, 2003

Three dimensional CMOS devices and integrated circuits.

Mei-Kei Ieong, Kathryn W. Guarini, Victor Chan, Kerry Bernstein, Rajiv V. Joshi, Jakub Kedzierski, Wilfred Haensch

Proceedings of the IEEE Custom Integrated Circuits Conference, 2003

2002

High Performance Double-Gate Device Technology Challenges and Opportunities (invited).

Meikei Leong, H.-S. Philip Wong, Edward J. Nowak, Jakub Kedzierski, Erin C. Jones

Proceedings of the 3rd International Symposium on Quality of Electronic Design, 2002