Jakub Janicki

According to our database, Jakub Janicki authored at least 15 papers between 2010 and 2024.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2024

Adaptive Diagnosis Points for 100% Chain Diagnosis Coverage.

Wu-Tung Cheng, Manish Sharma, Xin Yang, Artur Stelmach, Szczepan Urban, Jakub Janicki, Preston McWithey

Proceedings of the IEEE International Test Conference, 2024

2023

Predicting the Resolution of Scan Diagnosis.

Manoj Devendhiran, Jakub Janicki, Szczepan Urban, Manish Sharma, Jayant D'Souza

Proceedings of the IEEE International Test Conference, 2023

2022

Industry Evaluation of Reversible Scan Chain Diagnosis.

Soumya Mittal, Szczepan Urban, Kun Young Chung, Jakub Janicki, Wu-Tung Cheng, Martin Parley, Manish Sharma, Shaun Nicholson

Proceedings of the IEEE International Test Conference, 2022

2020

Scan Chain Diagnosis-Driven Test Response Compactor.

Jakub Janicki, Grzegorz Mrugalski, Artur Stelmach, Szczepan Urban

Proceedings of the 29th IEEE Asian Test Symposium, 2020

2019

Non-Adaptive Pattern Reordering to Improve Scan Chain Diagnostic Resolution.

Yu Huang, Jakub Janicki, Szczepan Urban

Proceedings of the 24th IEEE European Test Symposium, 2019

2015

Scan Test Bandwidth Management for Ultralarge-Scale System-on-Chip Architectures.

Wu-Tung Cheng, Yan Dong, Grady Giles, Yu Huang, Jakub Janicki, Mark Kassab, Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer

IEEE Trans. Very Large Scale Integr. Syst., 2015

2014

Erratum to "Test Time Reduction in EDT Bandwidth Management for SoC Designs".

Jakub Janicki, Mark Kassab, Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014

High-Speed Serial Embedded Deterministic Test for System-on-Chip Designs.

Maciej Trawka, Grzegorz Mrugalski, Nilanjan Mukherjee, Artur Pogiel, Janusz Rajski, Jakub Janicki, Jerzy Tyszer

Proceedings of the 23rd IEEE Asian Test Symposium, 2014

2013

Test Time Reduction in EDT Bandwidth Management for SoC Designs.

Jakub Janicki, Mark Kassab, Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013

EDT bandwidth management - Practical scenarios for large SoC designs.

Jakub Janicki, Jerzy Tyszer, Wu-Tung Cheng, Yu Huang, Mark Kassab, Nilanjan Mukherjee, Janusz Rajski, Yan Dong, Grady Giles

Proceedings of the 2013 IEEE International Test Conference, 2013

2012

EDT Bandwidth Management in SoC Designs.

Jakub Janicki, Mark Kassab, Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012

Bandwidth-aware test compression logic for SoC designs.

Jakub Janicki, Jerzy Tyszer, Grzegorz Mrugalski, Janusz Rajski

Proceedings of the 17th IEEE European Test Symposium, 2012

2011

EDT channel bandwidth management in SoC designs with pattern-independent test access mechanism.

Jakub Janicki, Jerzy Tyszer, Avijit Dutta, Mark Kassab, Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski

Proceedings of the 2011 IEEE International Test Conference, 2011

Low Test Data Volume Low Power At-Speed Delay Tests Using Clock-Gating.

Elham K. Moghaddam, Janusz Rajski, Sudhakar M. Reddy, Jakub Janicki

Proceedings of the 20th IEEE Asian Test Symposium, 2011

2010

Dynamic channel allocation for higher EDT compression in SoC designs.

Mark Kassab, Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, Jakub Janicki, Jerzy Tyszer

Proceedings of the 2011 IEEE International Test Conference, 2010