Jakob Lechner

According to our database, Jakob Lechner authored at least 18 papers between 2009 and 2020.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2020

Formal Verification of Spacecraft Control Programs.

Georgy Lukyanov, Andrey Mokhov, Jakob Lechner

ACM Trans. Embed. Comput. Syst., 2020

2019

Formal verification of spacecraft control programs (experience report).

Andrey Mokhov, Georgy Lukyanov, Jakob Lechner

Proceedings of the 12th ACM SIGPLAN International Symposium on Haskell, 2019

2018

Formal Verification of Spacecraft Control Programs Using a Metalanguage for State Transformers.

Andrey Mokhov, Georgy Lukyanov, Jakob Lechner

CoRR, 2018

State Recovery for Coarse-Grain TMR Designs in FPGAs Using Partial Reconfiguration.

Markus Schütz, Andreas Steininger, Florian Huemer, Jakob Lechner

Proceedings of the 2018 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2018

2016

A new coding scheme for fault tolerant 4-phase delay-insensitive codes.

Florian Huemer, Jakob Lechner, Andreas Steininger

Proceedings of the 34th IEEE International Conference on Computer Design, 2016

2015

Methods for analysing and improving the fault resilience of delay-insensitive codes.

Jakob Lechner, Andreas Steininger, Florian Huemer

Proceedings of the 33rd IEEE International Conference on Computer Design, 2015

2014

Protection of Muller-Pipelines from transient faults.

Syed Rameez Naqvi, Jakob Lechner, Andreas Steininger

Proceedings of the Fifteenth International Symposium on Quality Electronic Design, 2014

2013

An SET Tolerant Tree Arbiter Cell.

Syed Rameez Naqvi, Andreas Steininger, Jakob Lechner

Proceedings of the 19th IEEE International Symposium on Asynchronous Circuits and Systems, 2013

Modular Redundancy in a GALS System Using Asynchronous Recovery Links.

Jakob Lechner, Varadan Savulimedu Veeravalli

Proceedings of the 19th IEEE International Symposium on Asynchronous Circuits and Systems, 2013

2012

Muller C-Element Metastability Containment.

Thomas Polzer, Andreas Steininger, Jakob Lechner

Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2012

A Generic Architecture for Robust Asynchronous Communication Links.

Jakob Lechner, Robert Najvirt

Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2012

Protecting pipelined asynchronous communication channels against single event upsets.

Jakob Lechner, Martin Lampacher

Proceedings of the 30th International IEEE Conference on Computer Design, 2012

Designing Robust GALS Circuits with Triple Modular Redundancy.

Jakob Lechner

Proceedings of the 2012 Ninth European Dependable Computing Conference, 2012

A Robust Asynchronous Interfacing Scheme with Four-Phase Dual-Rail Coding.

Jakob Lechner, Martin Lampacher, Thomas Polzer

Proceedings of the 12th International Conference on Application of Concurrency to System Design, 2012

2010

Low Latency Recovery from Transient Faults for Pipelined Processor Architectures.

Marcus Jeitler, Jakob Lechner

Proceedings of the 13th Euromicro Conference on Digital System Design, 2010

Enhancing pipelined processor architectures with fast autonomous recovery of transient faults.

Marcus Jeitler, Jakob Lechner, Andreas Steininger

Proceedings of the 13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2010

2009

Speeding up Fault Injection for Asynchronous Logic by FPGA-Based Emulation.

Marcus Jeitler, Jakob Lechner

Proceedings of the ReConFig'09: 2009 International Conference on Reconfigurable Computing and FPGAs, 2009

Towards Comparing the Robustness of Synchronous and Asynchronous Circuits by Fault Injection.

Marcus Jeitler, Jakob Lechner

Proceedings of the Annual Doctoral Workshop on Mathematical and Engineering Methods in Computer Science, 2009