Jainaveen Sundaram

According to our database1, Jainaveen Sundaram authored at least 7 papers between 2021 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2024
LLaVaOLMoBitnet1B: Ternary LLM goes Multimodal!
CoRR, 2024

A 3.2GHz-15GHz Low Jitter Resonant Clock Featuring Rotary Traveling Wave Oscillators in Intel 4 CMOS for 3D Heterogeneous Multi-Die Systems.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits 2024, 2024

2023
CPU Microarchitectural Performance Analysis of SVT-AV1 Encoder.
Proceedings of the IEEE International Conference on Image Processing, 2023

2022
Resonant Rotary Clock Synchronization with Active and Passive Silicon Interposer.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

2021
A Reconfigurable Asynchronous SERDES for Heterogenous Chiplet Interconnects.
Proceedings of the 22nd International Symposium on Quality Electronic Design, 2021

Trends and Opportunities for SRAM Based In-Memory and Near-Memory Computation.
Proceedings of the 22nd International Symposium on Quality Electronic Design, 2021

A 93 TOPS/Watt Near-Memory Reconfigurable SAD Accelerator for HEVC/AV1/JEM Encoding.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021


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