Jai Menon
Affiliations:- University of Wisconsin
According to our database1,
Jai Menon
authored at least 9 papers
between 2012 and 2018.
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Collaborative distances:
Timeline
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Book In proceedings Article PhD thesis Dataset OtherLinks
Online presence:
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Bibliography
2018
Intel nGraph: An Intermediate Representation, Compiler, and Executor for Deep Learning.
CoRR, 2018
2015
ISA Wars: Understanding the Relevance of ISA being RISC or CISC to Performance, Power, and Energy on Modern Architectures.
ACM Trans. Comput. Syst., 2015
Enabling GPGPU Low-Level Hardware Explorations with MIAOW: An Open-Source RTL Implementation of a GPGPU.
ACM Trans. Archit. Code Optim., 2015
Proceedings of the 2015 IEEE Hot Chips 27 Symposium (HCS), 2015
Proceedings of the 2015 IEEE Symposium in Low-Power and High-Speed Chips, 2015
2014
Proceedings of the 2014 IEEE Hot Chips 26 Symposium (HCS), 2014
2013
Power struggles: Revisiting the RISC vs. CISC debate on contemporary ARM and x86 architectures.
Proceedings of the 19th IEEE International Symposium on High Performance Computer Architecture, 2013
2012
Proceedings of the 39th International Symposium on Computer Architecture (ISCA 2012), 2012