Jai Gopal Pandey

Abir J. Mondal

Proceedings of the 37th International Conference on VLSI Design and 23rd International Conference on Embedded Systems, 2024

Security Assessment of Rotation Countermeasure for Protection Against Fault Attacks.

[BibT_eX]

[DOI]

Proceedings of the 28th International Symposium on VLSI Design and Test, 2024

Emerging Frontiers and Limitations of Logic Locking for Secure IC Design.

[BibT_eX]

[DOI]

Proceedings of the 17th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2024

2023

Logic locking for IP security: A comprehensive analysis on challenges, techniques, and trends.

[BibT_eX]

[DOI]

Comput. Secur., June, 2023

An RTL Implementation of the Data Encryption Standard (DES).

[BibT_eX]

[DOI]

Ruby Kumari

CoRR, 2023

Security Evaluation of Lightweight SBoxes.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Smart Electronic Systems, 2023

PHAc: Posit Hardware Accelerator for Efficient Arithmetic Logic Operations.

[BibT_eX]

[DOI]

Proceedings of the Next Generation Arithmetic - 4th International Conference, 2023

LOKI: A Secure FPGA Prototyping of IoT IP with Lightweight Logic Locking.

[BibT_eX]

[DOI]

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2023

2022

An Overlap-and-Add Based Time Domain Acceleration of CNNs on FPGA-CPU Systems.

[BibT_eX]

[DOI]

Rudresh Pratap Singh

Shreyam Kumar

Proceedings of the VLSI Design and Test - 26th International Symposium, 2022

2021

GIFT cipher usage in image data security: hardware implementations, performance and statistical analyses.

[BibT_eX]

[DOI]

Apoorva Jangir

J. Real Time Image Process., 2021

An embedded FPGA-SoC framework and its usage in moving object tracking application.

[BibT_eX]

[DOI]

Des. Autom. Embed. Syst., 2021

A Hardware Generator for Posit Arithmetic and its FPGA Prototyping.

[BibT_eX]

[DOI]

Diksha Shekhawat

Apoorva Jangir

Proceedings of the 25th International Symposium on VLSI Design and Test, 2021

2020

A Highly Stable and Robust 7T SRAM Cell using Memristor.

[BibT_eX]

[DOI]

Sahan Panguluru

Proceedings of the 2020 24th International Symposium on VLSI Design and Test (VDAT), 2020

A Lightweight VLSI Architecture for RECTANGLE Cipher and its Implementation on an FPGA.

[BibT_eX]

[DOI]

Ayush Laddha

Sashwat Deb Samaddar

Proceedings of the 2020 24th International Symposium on VLSI Design and Test (VDAT), 2020

A Unified Architecture for AES/PRESENT Ciphers and its Usage in an SoC Environment.

[BibT_eX]

[DOI]

Sanskriti Gupta

Proceedings of the 11th IEEE Latin American Symposium on Circuits & Systems, 2020

2019

An ultra-low power, reconfigurable, aging resilient RO PUF for IoT applications.

[BibT_eX]

[DOI]

Sajid Khan

Ambika Prasad Shah

Neha Gupta

Shailesh Singh Chouhan

Microelectron. J., 2019

Hardware architectures for PRESENT block cipher and their FPGA implementations.

[BibT_eX]

[DOI]

Tarun Goel

IET Circuits Devices Syst., 2019

A Novel Design of SRAM Using Memristors at 45 nm Technology.

[BibT_eX]

[DOI]

Victor Jeffry Louis

Proceedings of the VLSI Design and Test - 23rd International Symposium, 2019

Dual-Edge Triggered Lightweight Implementation of AES for IoT Security.

[BibT_eX]

[DOI]

Sajid Khan

Neha Gupta

Abhinav Vishwakarma

Shailesh Singh Chouhan

Proceedings of the VLSI Design and Test - 23rd International Symposium, 2019

An Ultra Low Power AES Architecture for IoT.

[BibT_eX]

[DOI]

Proceedings of the VLSI Design and Test - 23rd International Symposium, 2019

An RNS Implementation of the Elliptic Curve Cryptography for IoT Security.

[BibT_eX]

[DOI]

Chhavi Mitharwal

Proceedings of the First IEEE International Conference on Trust, 2019

2018

A High-Performance and Area-Efficient VLSI Architecture for the PRESENT Lightweight Cipher.

[BibT_eX]

[DOI]

Tarun Goel

Proceedings of the 31st International Conference on VLSI Design and 17th International Conference on Embedded Systems, 2018

A VLSI Architecture for the PRESENT Block Cipher with FPGA and ASIC Implementations.

[BibT_eX]

[DOI]

Raj Singh

Proceedings of the VLSI Design and Test - 22nd International Symposium, 2018

A High-Performance VLSI Architecture of the Present Cipher and its Implementations for SoCs.

[BibT_eX]

[DOI]

Proceedings of the 31st IEEE International System-on-Chip Conference, 2018

2017

An Efficient VLSI Architecture for PRESENT Block Cipher and Its FPGA Implementation.

[BibT_eX]

[DOI]

Tarun Goel

Proceedings of the VLSI Design and Test - 21st International Symposium, 2017

2015

An FPGA-Based Architecture for Local Similarity Measure for Image/Video Processing Applications.

[BibT_eX]

[DOI]

Proceedings of the 28th International Conference on VLSI Design, 2015

An embedded framework for accurate object localization using center of gravity measure with mean shift procedure.

[BibT_eX]

[DOI]

Proceedings of the 19th International Symposium on VLSI Design and Test, 2015

2014

A Novel Architecture for FPGA Implementation of Otsu's Global Automatic Image Thresholding Algorithm.

[BibT_eX]

[DOI]

Proceedings of the 2014 27th International Conference on VLSI Design, 2014

Architectures and algorithms for image and video processing using FPGA-based platform.

[BibT_eX]

[DOI]