Jagdeep Kaur Sahani
According to our database1,
Jagdeep Kaur Sahani
authored at least 5 papers
between 2019 and 2022.
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Bibliography
2022
A low jitter and fast locking all digital phase locked loop with flash based time to digital converter and gain calibrated voltage controlled oscillator.
Int. J. Circuit Theory Appl., 2022
A 1 μs Locking Time Dual Loop ADPLL with Foreground Calibration-Based 6 ps Resolution Flash TDC in 180 nm CMOS.
Circuits Syst. Signal Process., 2022
2020
A Wide Frequency Range Low Jitter Integer PLL with Switch and Inverter Based CP in 0.18 μm CMOS Technology.
J. Circuits Syst. Comput., 2020
A 2.3 mW Multi-Frequency Clock Generator with -137 dBc/Hz Phase Noise VCO in 180 nm Digital CMOS Technology.
J. Circuits Syst. Comput., 2020
2019
A High Resolution and Low Jitter 5-Bit Flash TDC Architecture for High Speed Intelligent Systems.
Proceedings of the Intelligent Systems and Applications, 2019