Jagannath Samanta
Orcid: 0000-0003-1168-1166
According to our database1,
Jagannath Samanta
authored at least 10 papers
between 2012 and 2023.
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Bibliography
2023
An Improved Single and Double-Adjacent Error Correcting Codec with Lower Decoding Overheads.
J. Signal Process. Syst., June, 2023
Construction Technique and Evaluation of High Performance t-bit Burst Error Correcting Codes for Protecting MCUs.
J. Circuits Syst. Comput., June, 2023
Comments on "New low power and fast SEC-DAEC and SEC-DAEC-TAEC codes for memories in space application".
Integr., 2023
2022
J. Circuits Syst. Comput., 2022
2020
Lower complexity error location detection block of adjacent error correcting decoder for SRAMs.
IET Comput. Digit. Tech., 2020
2019
Comments on "a novel approach of error detection and correction for efficient energy in wireless networks".
Multim. Tools Appl., 2019
Fast and Power Efficient SEC-DED and SEC-DED-DAEC Codes in IoT based Wireless Sensor Networks.
Proceedings of the TENCON 2019, 2019
2018
2015
2012
Implementation of a New Offset Generator Block for the Low-Voltage, Low-Power Self Biased Threshold Voltage Extractor Circuit.
Proceedings of the Progress in VLSI Design and Test - 16th International Symposium, 2012