Jagadish Kotra

According to our database1, Jagadish Kotra authored at least 32 papers between 2013 and 2024.

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Bibliography

2024
Counter-light Memory Encryption.
Proceedings of the 51st ACM/IEEE Annual International Symposium on Computer Architecture, 2024

2023
TRIM: crossTalk-awaRe qubIt Mapping for multiprogrammed quantum systems.
Proceedings of the IEEE International Conference on Quantum Software, 2023


2022
Data Convection: A GPU-Driven Case Study for Thermal-Aware Data Placement in 3D DRAMs.
Proc. ACM Meas. Anal. Comput. Syst., 2022

Eager Memory Cryptography in Caches.
Proceedings of the 55th IEEE/ACM International Symposium on Microarchitecture, 2022

Fine-Granular Computation and Data Layout Reorganization for Improving Locality.
Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design, 2022

Athena: An Early-Fetch Architecture to Reduce on-Chip Page Walk Latencies.
Proceedings of the International Conference on Parallel Architectures and Compilation Techniques, 2022

2021
Increasing GPU Translation Reach by Leveraging Under-Utilized On-Chip Resources.
Proceedings of the MICRO '21: 54th Annual IEEE/ACM International Symposium on Microarchitecture, 2021

Quantifying Server Memory Frequency Margin and Using It to Improve Performance in HPC Systems.
Proceedings of the 48th ACM/IEEE Annual International Symposium on Computer Architecture, 2021

2020
Optimization of Intercache Traffic Entanglement in Tagless Caches With Tiling Opportunities.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

DSM: A Case for Hardware-Assisted Merging of DRAM Rows with Same Content.
Proc. ACM Meas. Anal. Comput. Syst., 2020

Centaur: A Novel Architecture for Reliable, Low-Wear, High-Density 3D NAND Storage.
Proc. ACM Meas. Anal. Comput. Syst., 2020

Improving the Utilization of Micro-operation Caches in x86 Processors.
Proceedings of the 53rd Annual IEEE/ACM International Symposium on Microarchitecture, 2020

PreFAM: Understanding the Impact of Prefetching in Fabric-Attached Memory Architectures.
Proceedings of the MEMSYS 2020: The International Symposium on Memory Systems, 2020

2019
CASH: compiler assisted hardware design for improving DRAM energy efficiency in CNN inference.
Proceedings of the International Symposium on Memory Systems, 2019

SOML Read: Rethinking the Read Operation Granularity of 3D NAND SSDs.
Proceedings of the Twenty-Fourth International Conference on Architectural Support for Programming Languages and Operating Systems, 2019

2018
A Learning-Guided Hierarchical Approach for Biomedical Image Segmentation.
Proceedings of the 31st IEEE International System-on-Chip Conference, 2018

Enhancing computation-to-core assignment with physical location information.
Proceedings of the 39th ACM SIGPLAN Conference on Programming Language Design and Implementation, 2018

CHAMELEON: A Dynamically Reconfigurable Heterogeneous Memory System.
Proceedings of the 51st Annual IEEE/ACM International Symposium on Microarchitecture, 2018

MDACache: Caching for Multi-Dimensional-Access Memories.
Proceedings of the 51st Annual IEEE/ACM International Symposium on Microarchitecture, 2018

PEN: Design and Evaluation of Partial-Erase for 3D NAND-Based High Density SSDs.
Proceedings of the 16th USENIX Conference on File and Storage Technologies, 2018

2017
Quantifying the Potential Benefits of On-chip Near-Data Computing in Manycore Processors.
Proceedings of the 25th IEEE International Symposium on Modeling, 2017

Congestion-aware memory management on NUMA platforms: A VMware ESXi case study.
Proceedings of the 2017 IEEE International Symposium on Workload Characterization, 2017

Hardware-Software Co-design to Mitigate DRAM Refresh Overheads: A Case for Refresh-Aware Process Scheduling.
Proceedings of the Twenty-Second International Conference on Architectural Support for Programming Languages and Operating Systems, 2017

POSTER: Location-Aware Computation Mapping for Manycore Processors.
Proceedings of the 26th International Conference on Parallel Architectures and Compilation Techniques, 2017

2016
Improving bank-level parallelism for irregular applications.
Proceedings of the 49th Annual IEEE/ACM International Symposium on Microarchitecture, 2016

Re-NUCA: A Practical NUCA Architecture for ReRAM Based Last-Level Caches.
Proceedings of the 2016 IEEE International Parallel and Distributed Processing Symposium, 2016

Cache-Aware Approximate Computing for Decision Tree Learning.
Proceedings of the 2016 IEEE International Parallel and Distributed Processing Symposium Workshops, 2016

2015
Thermal-Aware Application Scheduling on Device-Heterogeneous Embedded Architectures.
Proceedings of the 28th International Conference on VLSI Design, 2015

Phase Detection with Hidden Markov Models for DVFS on Many-Core Processors.
Proceedings of the 35th IEEE International Conference on Distributed Computing Systems, 2015

Network footprint reduction through data access and computation placement in NoC-based manycores.
Proceedings of the 52nd Annual Design Automation Conference, 2015

2013
Meeting midway: Improving CMP performance with memory-side prefetching.
Proceedings of the 22nd International Conference on Parallel Architectures and Compilation Techniques, 2013


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