Jafar Savoj

According to our database, Jafar Savoj authored at least 23 papers between 2001 and 2015.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2015

A 0.5-16.3 Gb/s Fully Adaptive Flexible-Reach Transceiver for FPGA in 20 nm CMOS.

Yohan Frans, Declan Carey, Marc Erett, Hesam Amir Aslanzadeh, Wayne Y. Fang, Didem Turker, Anup P. Jose, Adebabay Bekele, Jay Im, Parag Upadhyaya, Zhaoyin Daniel Wu, Kenny C.-H. Hsieh, Jafar Savoj, Ken Chang

IEEE J. Solid State Circuits, 2015

3.3 A 0.5-to-32.75Gb/s flexible-reach wireline transceiver in 20nm CMOS.

Parag Upadhyaya, Jafar Savoj, Fu-Tai An, Ade Bekele, Anup P. Jose, Bruce Xu, Zhaoyin Daniel Wu, Didem Turker, Hesam Amir Aslanzadeh, Hiva Hedayati, Jay Im, Siok-Wei Lim, Stanley Chen, Toan Pham, Yohan Frans, Ken Chang

Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015

2014

2.8 A pulse-position-modulation phase-noise-reduction technique for a 2-to-16GHz injection-locked ring oscillator in 20nm CMOS.

Jun-Chau Chien, Parag Upadhyaya, Howard Jung, Stanley Chen, Wayne Fang, Ali M. Niknejad, Jafar Savoj, Ken Chang

Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014

Wideband flexible-reach techniques for a 0.5-16.3Gb/s fully-adaptive transceiver in 20nm CMOS.

Jafar Savoj, Hesam Amir Aslanzadeh, Declan Carey, Marc Erett, Wayne Fang, Yohan Frans, Kenny C.-H. Hsieh, Jay Im, Anup P. Jose, Didem Turker, Parag Upadhyaya, Zhaoyin Daniel Wu, Ken Chang

Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, 2014

2013

A Low-Power 0.5-6.6 Gb/s Wireline Transceiver Embedded in Low-Cost 28 nm FPGAs.

Jafar Savoj, Kenny C.-H. Hsieh, Fu-Tai An, J. Gong, Jay Im, Xuewen Jiang, Anup P. Jose, Vassili Kireev, Siok-Wei Lim, Arianne Roldan, D. Z. Turker, Parag Upadhyaya, Zhaoyin Daniel Wu, Ken Chang

IEEE J. Solid State Circuits, 2013

Session 10 overview: Analog techniques.

Jafar Savoj, Chris Mangelsdorf

Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013

F6: Mixed-signal/RF design and modeling in next-generation CMOS.

Boris Murmann, Jafar Savoj, Piet Wambacq, Jieh-Tsorng Wu

Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013

2012

A wide common-mode fully-adaptive multi-standard 12.5Gb/s backplane transceiver in 28nm CMOS.

Jafar Savoj, Kenny C.-H. Hsieh, Parag Upadhyaya, Fu-Tai An, Ade Bekele, Stanley Chen, Xuewen Jiang, Kang Wei Lai, Chi Fung Poon, Aman Sewani, Didem Turker, Karthik Venna, Zhaoyin Daniel Wu, Bruce Xu, Elad Alon, Ken Chang

Proceedings of the Symposium on VLSI Circuits, 2012

Session 21 overview: Analog techniques: Analog subcommittee.

Jafar Savoj, Chris Mangelsdorf

Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012

Technologies that could change the world - You decide!

Jed Hurwitz, Jafar Savoj

Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012

Design of high-speed wireline transceivers for backplane communications in 28nm CMOS.

Jafar Savoj, Kenny C.-H. Hsieh, Parag Upadhyaya, Fu-Tai An, Jay Im, Xuewen Jiang, Jalil Kamali, Kang Wei Lai, Zhaoyin Daniel Wu, Elad Alon, Ken Chang

Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, 2012

2011

Introduction to the Special Issue on the 2011 IEEE International Solid-State Circuits Conference.

Jafar Savoj, Yiannos Manoli, Hooman Darabi, Yorgos Palaskas, Michael Moyal

IEEE J. Solid State Circuits, 2011

High-speed transceivers: Standards, challenges, and future.

Ali Sheikholeslami, Franz Dielacher, Miki Moyal, Jafar Savoj, John T. Stonick, Takuji Yamamoto

Proceedings of the IEEE International Solid-State Circuits Conference, 2011

2008

A 12-GS/s Phase-Calibrated CMOS Digital-to-Analog Converter for Backplane Communications.

Jafar Savoj, Aliazam Abbasfar, Amir Amirkhany, Metha Jeeradit, Bruno W. Garlepp

IEEE J. Solid State Circuits, 2008

A 24 Gb/s Software Programmable Analog Multi-Tone Transmitter.

Amir Amirkhany, Aliazam Abbasfar, Jafar Savoj, Metha Jeeradit, Bruno W. Garlepp, Ravi T. Kollipara, Vladimir Stojanovic, Mark Horowitz

IEEE J. Solid State Circuits, 2008

2007

A new technique for characterization of digital-to-analog converters in high-speed systems.

Jafar Savoj, Ali-Azam Abbasfar, Amir Amirkhany, Bruno W. Garlepp, Mark A. Horowitz

Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

Time-Variant Characterization and Compensation of Wideband Circuits.

Amir Amirkhany, Ali-Azam Abbasfar, Jafar Savoj, Mark A. Horowitz

Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, 2007

2005

Introduction to the Special Issue on the IEEE 2004 Custom Integrated Circuits Conference.

Albert Z. H. Wang, Sreedhar Natarajan, Jafar Savoj

IEEE J. Solid State Circuits, 2005

Will continued process-node shrinks kill high-performance analog design?

Jafar Savoj, David Rich, Brett Forejt, Peter R. Kinget, Un-Ku Moon, Modest M. Oprysko, Behzad Razavi, Hisashi (Sam) Shichijo, Albert Z. Wang

Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005

Clocking circuits for wireline communications.

Jafar Savoj, Ramesh Harjani

Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005

2003

A 10-Gb/s CMOS clock and data recovery circuit with a half-rate binary phase/frequency detector.

Jafar Savoj, Behzad Razavi

IEEE J. Solid State Circuits, 2003

2001

A 10-Gb/s CMOS clock and data recovery circuit with a half-rate linear phase detector.

Jafar Savoj, Behzad Razavi

IEEE J. Solid State Circuits, 2001

Design of Half-Rate Clock and Data Recovery Circuits for Optical Communication Systems.

Jafar Savoj, Behzad Razavi

Proceedings of the 38th Design Automation Conference, 2001