Jaeyun Yi
Orcid: 0000-0002-2940-9307
According to our database1,
Jaeyun Yi
authored at least 6 papers
between 2023 and 2024.
Collaborative distances:
Collaborative distances:
Timeline
2023
2024
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Bibliography
2024
First Demonstration of Fully Integrated 16 nm Half-Pitch Selector Only Memory (SOM) for Emerging CXL Memory.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits 2024, 2024
Improvement of MAC Accuracy using Oxygen Diffusion Barriers in Resistive Synaptic Cell Arrays.
Proceedings of the IEEE International Memory Workshop, 2024
Modeling and Demonstration for Multi-level Weight Conductance in Computational FeFET Memory Cell.
Proceedings of the IEEE International Memory Workshop, 2024
Realistic Noise-aware Training as a Component of the Holistic ACiM Development Platform.
Proceedings of the IEEE International Memory Workshop, 2024
2023
The Compact Support Property for Solutions to the Stochastic Partial Differential Equations with Colored Noise.
SIAM J. Math. Anal., December, 2023
The chalcogenide-based memory technology continues: beyond 20nm 4-deck 256Gb cross-point memory.
Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023