Jaeyong Chung

According to our database, Jaeyong Chung authored at least 53 papers between 2003 and 2024.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2024

Factored Systolic Arrays Based on Radix-8 Multiplication for Machine Learning Acceleration.

Kashif Inayat, Inayat Ullah, Jaeyong Chung

IEEE Trans. Very Large Scale Integr. Syst., July, 2024

2023

AGD: A Learning-based Optimization Framework for EDA and its Application to Gate Sizing.

Phuoc Pham, Jaeyong Chung

Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023

Quickloop: An Efficient, FPGA-Accelerated Exploration of Parameterized DNN Accelerators.

Tayyeb Mahmood, Kashif Inayat, Jaeyong Chung

Proceedings of the 32nd International Conference on Parallel Architectures and Compilation Techniques, 2023

2022

Hybrid Accumulator Factored Systolic Array for Machine Learning Acceleration.

Kashif Inayat, Jaeyong Chung

IEEE Trans. Very Large Scale Integr. Syst., 2022

2021

Training Multi-Bit Quantized and Binarized Networks with a Learnable Symmetric Quantizer.

Phuoc Pham, Jacob A. Abraham, Jaeyong Chung

IEEE Access, 2021

2020

ER-TCAM: A Soft-Error-Resilient SRAM-Based Ternary Content-Addressable Memory for FPGAs.

Inayat Ullah, Joon-Sung Yang, Jaeyong Chung

IEEE Trans. Very Large Scale Integr. Syst., 2020

Virtualization-Based Efficient TSV Repair for 3-D Integrated Circuits.

Muhammad Imran, Hyunseung Han, Jooho Kim, Taehyun Kwon, Jaeyong Chung, Joon-Sung Yang

IEEE Access, 2020

Reliable and Lightweight PUF-based Key Generation using Various Index Voting Architecture.

Jeong-Hyeon Kim, Ho-Jun Jo, Kyung-Kuk Jo, Sung-Hee Cho, Jaeyong Chung, Joon-Sung Yang

Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

Factored Radix-8 Systolic Array for Tensor Processing.

Inayat Ullah, Kashif Inayat, Joon-Sung Yang, Jaeyong Chung

Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020

2019

Weight Partitioning for Dynamic Fixed-Point Neuromorphic Computing Systems.

Yongshin Kang, Joon-Sung Yang, Jaeyong Chung

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019

Simplifying Deep Neural Networks for FPGA-Like Neuromorphic Systems.

Jaeyong Chung, Taehwan Shin, Joon-Sung Yang

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019

DeepRT: predictable deep learning inference for cyber-physical systems.

Woochul Kang, Jaeyong Chung

Real Time Syst., 2019

Power- and Time-Aware Deep Learning Inference for Mobile Embedded Devices.

Woochul Kang, Jaeyong Chung

IEEE Access, 2019

Physical Workout Classification Using Wrist Accelerometer Data by Deep Convolutional Neural Networks.

Pilyeong Jeong, Mungyeong Choe, Nahyeong Kim, Jaehyun Park, Jaeyong Chung

IEEE Access, 2019

2018

Mitigating Observability Loss of Toggle-Based X-Masking via Scan Chain Partitioning.

Sae-Eun Kim, Jaeyong Chung, Joon-Sung Yang

IEEE Trans. Computers, 2018

READ: Reliability Enhancement in 3D-Memory Exploiting Asymmetric SER Distribution.

Hyunseung Han, Jaeyong Chung, Joon-Sung Yang

IEEE Trans. Computers, 2018

Dynamic Fixed-Point Design of Neuromorphic Computing Systems.

Yongshin Kang, Jaeyong Chung

IEICE Trans. Electron., 2018

New library development method by FSM based cell pattern extraction.

Byung-Su Kim, Tae Hee Han, Joon-Sung Yang, Jaeyong Chung

IEICE Electron. Express, 2018

2017

Energy-efficient response time management for embedded databases.

Woochul Kang, Jaeyong Chung

Real Time Syst., 2017

Exploiting Sparse Activation for Low-Power Design of Synchronous Neuromorphic Systems.

Jaeyong Chung, Woochul Kang

IEICE Trans. Electron., 2017

A dynamic fixed-point representation for neuromorphic computing systems.

Yongshin Kang, Jaeyong Chung

Proceedings of the International SoC Design Conference, 2017

Synthesis of activation-parallel convolution structures for neuromorphic architectures.

Seban Kim, Jaeyong Chung

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

2016

Defect Diagnosis via Segment Delay Learning.

Jaeyong Chung, Woochul Kang

IEEE Trans. Very Large Scale Integr. Syst., 2016

Live demonstration: Real-time image classification on a neuromorphic computing system with zero off-chip memory access.

Taehwan Shin, Yongshin Kang, Seungho Yang, Seban Kim, Jaeyong Chung

Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

Simplifying deep neural networks for neuromorphic architectures.

Jaeyong Chung, Taehwan Shin

Proceedings of the 53rd Annual Design Automation Conference, 2016

2015

Segment Delay Learning From Quantized Path Delay Measurements.

Jaeyong Chung, Jibum Kim

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015

Bit-Width Optimization by Divide-and-Conquer for Fixed-Point Digital Signal Processing Systems.

Jaeyong Chung, Lok-Won Kim

IEEE Trans. Computers, 2015

QoS Management for Embedded Databases in Multicore-Based Embedded Systems.

Woochul Kang, Jaeyong Chung

Mob. Inf. Syst., 2015

Delay Defect Diagnosis Methodology Using Path Delay Measurements.

Eun Jung Jang, Jaeyong Chung, Jacob A. Abraham

IEICE Trans. Electron., 2015

Untangling polygonal and polyhedral meshes via mesh optimization.

Jibum Kim, Jaeyong Chung

Eng. Comput., 2015

INsight: A Neuromorphic Computing System for Evaluation of Large Neural Networks.

Jaeyong Chung, Taehwan Shin, Yongshin Kang

CoRR, 2015

2014

3-D Probe: Low-Cost Variation Modeling Using Intertest-Item Correlations.

Jaeyong Chung, Yonghyun Kim, Joon-Sung Yang

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014

2013

A Built-In Repair Analyzer With Optimal Repair Rate for Word-Oriented Memories.

Jaeyong Chung, Joonsung Park, Jacob A. Abraham

IEEE Trans. Very Large Scale Integr. Syst., 2013

Concurrent Path Selection Algorithm in Statistical Timing Analysis.

Jaeyong Chung, Jacob A. Abraham

IEEE Trans. Very Large Scale Integr. Syst., 2013

2012

Testability-Driven Statistical Path Selection.

Jaeyong Chung, Jinjun Xiong, Vladimir Zolotov, Jacob A. Abraham

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012

Path Criticality Computation in Parameterized Statistical Timing Analysis Using a Novel Operator.

Jaeyong Chung, Jinjun Xiong, Vladimir Zolotov, Jacob A. Abraham

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012

On Computing Criticality in Refactored Timing Graphs.

Jaeyong Chung, Jacob A. Abraham

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012

Refactoring of Timing Graphs and Its Use in Capturing Topological Correlation in SSTA.

Jaeyong Chung, Jacob A. Abraham

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012

Temporal Presence Variation in Immersive Computer Games.

Jaeyong Chung, Henry J. Gardner

Int. J. Hum. Comput. Interact., 2012

2011

Off-Chip Skew Measurement and Compensation Module (SMCM) Design for Built-Off Test Chip.

Kihyuk Han, Joonsung Park, Jae Wook Lee, Jaeyong Chung, Eonjo Byun, Cheol-Jong Woo, Sejang Oh, Jacob A. Abraham

J. Electron. Test., 2011

Post-Silicon Timing Validation Method Using Path Delay Measurements.

Eun Jung Jang, Jaeyong Chung, Anne E. Gattiker, Sani R. Nassif, Jacob A. Abraham

Proceedings of the 20th IEEE Asian Test Symposium, 2011

Path criticality computation in parameterized statistical timing analysis.

Jaeyong Chung, Jinjun Xiong, Vladimir Zolotov, Jacob A. Abraham

Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011

2010

Reducing test time and area overhead of an embedded memory array built-in repair analyzer with optimal repair rate.

Jaeyong Chung, Joonsung Park, Jacob A. Abraham, Eonjo Byun, Cheol-Jong Woo

Proceedings of the 28th IEEE VLSI Test Symposium, 2010

A Built-In Self-Test scheme for high speed I/O using cycle-by-cycle edge control.

Hyunjin Kim, Jaeyong Chung, Jacob A. Abraham, Eonjo Byun, Cheol-Jong Woo

Proceedings of the 15th European Test Symposium, 2010

At-speed Test of High-Speed DUT Using Built-Off Test Interface.

Joonsung Park, Jae Wook Lee, Jaeyong Chung, Kihyuk Han, Jacob A. Abraham, Eonjo Byun, Cheol-Jong Woo, Sejang Oh

Proceedings of the 19th IEEE Asian Test Symposium, 2010

2009

Recursive Path Selection for Delay Fault Testing.

Jaeyong Chung, Jacob A. Abraham

Proceedings of the 27th IEEE VLSI Test Symposium, 2009

Measuring temporal variation in presence during game playing.

Jaeyong Chung, Henry J. Gardner

Proceedings of the 8th International Conference on Virtual Reality Continuum and its Applications in Industry, 2009

A hierarchy of subgraphs underlying a timing graph and its use in capturing topological correlation in SSTA.

Jaeyong Chung, Jacob A. Abraham

Proceedings of the 2009 International Conference on Computer-Aided Design, 2009

LFSR-Based Performance Characterization of Nonlinear Analog and Mixed-Signal Circuits.

Joonsung Park, Jaeyong Chung, Jacob A. Abraham

Proceedings of the Eighteentgh Asian Test Symposium, 2009

2006

A Dynamic Load Balancing for Massive Multiplayer Online Game Server.

Jungyoul Lim, Jaeyong Chung, Jin Ryong Kim, Kwanghyun Shim

Proceedings of the Entertainment Computing, 2006

Color Object Tracking System for Interactive Entertainment Applications.

Jaeyong Chung, Kwanghyun Shim

Proceedings of the 2006 IEEE International Conference on Acoustics Speech and Signal Processing, 2006

2004

VENUS: The Online Game Simulator Using Massively Virtual Clients.

YungWoo Jung, Bum-Hyun Lim, Kwanghyun Sim, Hunjoo Lee, Ilkyu Park, Jaeyong Chung, Jihong Lee

Proceedings of the Systems Modeling and Simulation: Theory and Applications, 2004

2003

Driving Virtual Human using the Hybrid of Position-based and Angle-based Control Mode.

Jaeyong Chung, Gwanghyun Shim, Byungtae Choi

Proceedings of the IASTED International Conference on Modelling, Simulation and Optimization, 2003