Jaewon Park
Orcid: 0000-0002-5704-726X
According to our database1,
Jaewon Park
authored at least 14 papers
between 2006 and 2023.
Collaborative distances:
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Bibliography
2023
A 16 GB 1024 GB/s HBM3 DRAM With Source-Synchronized Bus Design and On-Die Error Control Scheme for Enhanced RAS Features.
IEEE J. Solid State Circuits, 2023
2022
A 16 GB 1024 GB/s HBM3 DRAM with On-Die Error Control Scheme for Enhanced RAS Features.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022
2021
Optimization of PTFE Coating on PDMS Surfaces for Inhibition of Hydrophobic Molecule Absorption for Increased Optical Detection Sensitivity.
Sensors, 2021
Detection of Particulate Matters with a Field-Portable Microscope Using Side-Illuminated Total Internal Reflection.
Sensors, 2021
A 16-GB 640-GB/s HBM2E DRAM With a Data-Bus Window Extension Technique and a Synergetic On-Die ECC Scheme.
IEEE J. Solid State Circuits, 2021
IEEE Access, 2021
2020
Proceedings of the 26th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications, 2020
22.1 A 1.1V 16GB 640GB/s HBM2E DRAM with a Data-Bus Window-Extension Technique and a Synergetic On-Die ECC Scheme.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020
Proceedings of the International Conference on Information and Communication Technology Convergence, 2020
2018
A Three-Dimensional Arrayed Microfluidic Blood-Brain Barrier Model With Integrated Electrical Sensor Array.
IEEE Trans. Biomed. Eng., 2018
2016
2014
Evaluation of Large-Sized LCD Touch Panel Using Differential Sensing Circuit and Algorithm.
IEICE Trans. Inf. Syst., 2014
2006
IEICE Trans. Commun., 2006
Parallel Interference Cancellation Scheme Based on Sorting Method for a Multi-Carrier DS/CDMA System.
IEICE Trans. Commun., 2006