Jaeseung Choi

According to our database, Jaeseung Choi authored at least 9 papers between 2016 and 2023.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2023

A 14nm 128Mb Embedded MRAM Macro achieved the Best Figure-Of-Merit with 80MHz Read operation and 18.1Mb/mm² implementation at 0.64V.

Gyuseong Kang, Hyunjin Shin, Hyuntaek Jung, Sunkyu Lee, Jaeseung Choi, Sangyeop Baeck, Hyunsung Jung, Daeshik Kim, Sohee Hwang, Shinhee Han, Yongsung Ji, Sei Seung Yoon

Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023

2022

A 32Mb Embedded Flash Memory based on 28nm with the best Cell Efficiency and Robust Design achievement featuring 13.48Mb/mm² at 0.85V.

Hyunjin Shin, Sangkyung Won, Dohui Kim, Byunghun Choi, Gyusung Kim, Myeonghee Oh, Jaeseung Choi, Jongwook Kye

Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022

2021

A 28nm Embedded Flash Memory with 100MHz Read Operation and 7.42Mb/mm2 at 0.85V featuring for Automotive Application.

Hyunjin Shin, Myeonghee Oh, Jaeseung Choi, Taejoong Song, Jongwook Kye

Proceedings of the 2021 Symposium on VLSI Circuits, Kyoto, Japan, June 13-19, 2021, 2021

5nm Low Power SRAM Featuring Dual-Rail Architecture with Voltage-Tracking Assist Circuit for 5G mobile application.

Sangyeop Baeck, Inhak Lee, Hoyoung Tang, Dongwook Seo, Jaeseung Choi, Taejoong Song, Jongwook Kye

Proceedings of the 2021 Symposium on VLSI Circuits, Kyoto, Japan, June 13-19, 2021, 2021

2019

A Voltage and Temperature Tracking SRAM Assist Supporting 740mV Dual-Rail Offset for Low-Power and High-Performance Applications in 7nm EUV FinFET Technology.

Inhak Lee, Hanwool Jeong, Sangyeop Baeck, Siddharth Gupta, Changnam Park, Dongwook Seo, Jaeseung Choi, Jaeyoung Kim, Hoon Kim, Jungmyung Kang, Sunyung Jang, Daeyoung Moon, Sangshin Han, Taehyung Kim, Jaehyun Lim, Younghwan Park, Hyejin Hwang, Jeonseung Kang, Taejoong Song

Proceedings of the IEEE International Solid- State Circuits Conference, 2019

2018

A 7nm FinFET SRAM using EUV lithography with dual write-driver-assist circuitry for low-voltage applications.

Taejoong Song, Jonghoon Jung, Woojin Rim, Hoonki Kim, Yongho Kim, Changnam Park, Jeongho Do, Sunghyun Park, Sungwee Cho, Hyuntaek Jung, Bongjae Kwon, Hyun-Su Choi, Jaeseung Choi, Jong Shik Yoon

Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018

2017

A 10 nm FinFET 128 Mb SRAM With Assist Adjustment System for Power, Performance, and Area Optimization.

Taejoong Song, Woojin Rim, Sunghyun Park, Yongho Kim, Giyong Yang, Hoonki Kim, Sanghoon Baek, Jonghoon Jung, Bongjae Kwon, Sungwee Cho, Hyuntaek Jung, Yongjae Choo, Jaeseung Choi

IEEE J. Solid State Circuits, 2017

12.2 A 7nm FinFET SRAM macro using EUV lithography for peripheral repair analysis.

Taejoong Song, Hoonki Kim, Woojin Rim, Yongho Kim, Sunghyun Park, Changnam Park, Minsun Hong, Giyong Yang, Jeongho Do, Jinyoung Lim, Seungyoung Lee, Ingyum Kim, Sanghoon Baek, Jonghoon Jung, Daewon Ha, Hyungsoon Jang, Taejung Lee, Chul-Hong Park, Bongjae Kwon, Hyuntaek Jung, Sungwee Cho, Yongjae Choo, Jaeseung Choi

Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017

2016

17.1 A 10nm FinFET 128Mb SRAM with assist adjustment system for power, performance, and area optimization.

Taejoong Song, Woojin Rim, Sunghyun Park, Yongho Kim, Jonghoon Jung, Giyong Yang, Sanghoon Baek, Jaeseung Choi, Bongjae Kwon, Yunwoo Lee, Sungbong Kim, Gyu-Hong Kim, Hyo-Sig Won, Ja-Hum Ku, Sunhom Steve Paak, E. S. Jung, Steve Sungho Park, Kinam Kim

Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016