Jaemin Jang

Orcid: 0000-0003-1503-9998

According to our database¹, Jaemin Jang authored at least 15 papers between 2012 and 2024.

Collaborative distances:

Dijkstra number² of four.
Erdős number³ of four.

Timeline

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On csauthors.net:

Bibliography

2024

13.4 A 48GB 16-High 1280GB/s HBM3E DRAM with All-Around Power TSV and a 6-Phase RDQS Scheme for TSV Area Optimization.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Solid-State Circuits Conference, 2024

2019

Sparse-Insertion Write Cache to Mitigate Write Disturbance Errors in Phase Change Memory.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2019

DC-PCM: Mitigating PCM Write Disturbance with Low Performance Overhead by Using Detection Cells.

[BibT_eX]

[DOI]

Jungwhan Choi

Jaemin Jang

Lee-Sup Kim

IEEE Trans. Computers, 2019

2018

Elaborate Refresh: A Fine Granularity Retention Management for Deep Submicron DRAMs.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2018

2017

In-DRAM Data Initialization.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2017

Rank-Level Parallelism in DRAM.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2017

Bank-Group Level Parallelism.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2017

Refresh-Aware Write Recovery Memory Controller.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2017

A new application-layer overlay platform for better connected vehicles.

[BibT_eX]

[DOI]

Jaemin Jang

Taemin Ahn

Junghee Han

Int. J. Distributed Sens. Networks, 2017

2016

A Delay Locked Loop With a Feedback Edge Combiner of Duty-Cycle Corrector With a 20%-80% Input Duty Cycle for SDRAMs.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2016

DRAM-Latency Optimization Inspired by Relationship between Row-Access Time and Refresh Timing.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2016

Q-DRAM: Quick-Access DRAM with Decoupled Restoring from Row-Activation.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2016

Energy Efficient Data Encoding in DRAM Channels Exploiting Data Value Similarity.

[BibT_eX]

[DOI]

Proceedings of the 43rd ACM/IEEE Annual International Symposium on Computer Architecture, 2016

2015

Multiple clone row DRAM: a low latency and area optimized DRAM.

[BibT_eX]

[DOI]

Proceedings of the 42nd Annual International Symposium on Computer Architecture, 2015

2012

A 1.2V 38nm 2.4Gb/s/pin 2Gb DDR4 SDRAM with bank group and ×4 half-page architecture.

[BibT_eX]

[DOI]

Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012

Jaemin Jang

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