Jaekyu Lee

Orcid: 0000-0002-0574-5381

According to our database1, Jaekyu Lee authored at least 37 papers between 2009 and 2024.

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Bibliography

2024
Data pipeline for real-time energy consumption data management and prediction.
Frontiers Big Data, 2024

2023
Construction Site Safety Management: A Computer Vision and Deep Learning Approach.
Sensors, January, 2023

RV-CURE: A RISC-V Capability Architecture for Full Memory Safety.
CoRR, 2023

Hardware-Assisted Code-Pointer Tagging for Forward-Edge Control-Flow Integrity.
IEEE Comput. Archit. Lett., 2023

Do Video Encoding Workloads Stress the Microarchitecture?
Proceedings of the IEEE International Symposium on Workload Characterization, 2023

2022
Channel Sampler in Hyperspectral Images for Vehicle Detection.
IEEE Geosci. Remote. Sens. Lett., 2022

2.45 e-RMS Low-Random-Noise, 598.5 mW Low-Power, and 1.2 kfps High-Speed 2-Mp Global Shutter CMOS Image Sensor With Pixel-Level ADC and Memory.
IEEE J. Solid State Circuits, 2022

Microarchitectural Performance Evaluation of AV1 Video Encoding Workloads.
Proceedings of the International IEEE Symposium on Performance Analysis of Systems and Software, 2022

Securing GPU via region-based bounds checking.
Proceedings of the ISCA '22: The 49th Annual International Symposium on Computer Architecture, New York, New York, USA, June 18, 2022

Design and analysis on low-power and low-noise single slope ADC for digital pixel sensors.
Proceedings of the Imaging Sensors and Systems 2022, online, January 15-26, 2022, 2022

TPC-C Benchmarking for ElasticSearch.
Proceedings of the IEEE International Conference on Big Data and Smart Computing, 2022

2021
A 2.6 e-rms Low-Random-Noise, 116.2 mW Low-Power 2-Mp Global Shutter CMOS Image Sensor with Pixel-Level ADC and In-Pixel Memory.
Proceedings of the 2021 Symposium on VLSI Circuits, Kyoto, Japan, June 13-19, 2021, 2021

7.9 1/2.74-inch 32Mpixel-Prototype CMOS Image Sensor with 0.64μ m Unit Pixels Separated by Full-Depth Deep-Trench Isolation.
Proceedings of the IEEE International Solid-State Circuits Conference, 2021

Re-establishing Fetch-Directed Instruction Prefetching: An Industry Perspective.
Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2021

A Complete and Fast Scraping Method for Collecting Tweets.
Proceedings of the IEEE International Conference on Big Data and Smart Computing, 2021

2020
Securing Branch Predictors with Two-Level Encryption.
ACM Trans. Archit. Code Optim., 2020

A Hand Gesture Recognition Method using Inertial Sensor for Rapid Operation on Embedded Device.
KSII Trans. Internet Inf. Syst., 2020

Rebasing Instruction Prefetching: An Industry Perspective.
IEEE Comput. Archit. Lett., 2020

Hardware-based Always-On Heap Memory Safety.
Proceedings of the 53rd Annual IEEE/ACM International Symposium on Microarchitecture, 2020

5.5 A 2.1e<sup>-</sup> Temporal Noise and -105dB Parasitic Light Sensitivity Backside-Illuminated 2.3µm-Pixel Voltage-Domain Global Shutter CMOS Image Sensor Using High-Capacity DRAM Capacitor Technology.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020

5.6 A 1/2.65in 44Mpixel CMOS Image Sensor with 0.7µm Pixels Fabricated in Advanced Full-Depth Deep-Trench Isolation Technology.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020

2019
Designing Hand Pose Aware Virtual Keyboard With Hand Drift Tolerance.
IEEE Access, 2019

TwohandsMusic: Multitask Learning-Based Egocentric Piano-Playing Gesture Recognition System for Two Hands.
Proceedings of the 2019 IEEE International Conference on Image Processing, 2019

2018
Supervisory control and data acquisition for Standalone Hybrid Power Generation Systems.
Sustain. Comput. Informatics Syst., 2018

A Study of Mobile Edge Computing System Architecture for Connected Car Media Services on Highway.
KSII Trans. Internet Inf. Syst., 2018

2015
GREEN Cache: Exploiting the Disciplined Memory Model of OpenCL on GPUs.
IEEE Trans. Computers, 2015

2014
Shared resource management for efficient heterogeneous computing.
PhD thesis, 2014

2013
Adaptive virtual channel partitioning for network-on-chip in heterogeneous architectures.
ACM Trans. Design Autom. Electr. Syst., 2013

Design space exploration of on-chip ring interconnection for a CPU-GPU heterogeneous architecture.
J. Parallel Distributed Comput., 2013

Consistent Sampling with Multi-, Pre- and Post-Filterings.
Int. J. Wavelets Multiresolution Inf. Process., 2013

2012
When Prefetching Works, When It Doesn't, and Why.
ACM Trans. Archit. Code Optim., 2012

DRAM Scheduling Policy for GPGPU Architectures Based on a Potential Function.
IEEE Comput. Archit. Lett., 2012

FLEXclusion: Balancing cache capacity and on-chip bandwidth via Flexible Exclusion.
Proceedings of the 39th International Symposium on Computer Architecture (ISCA 2012), 2012

TAP: A TLP-aware cache management policy for a CPU-GPU heterogeneous architecture.
Proceedings of the 18th IEEE International Symposium on High Performance Computer Architecture, 2012

2010
Irregular Sampling on Shift Invariant Spaces.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2010

Many-Thread Aware Prefetching Mechanisms for GPGPU Applications.
Proceedings of the 43rd Annual IEEE/ACM International Symposium on Microarchitecture, 2010

2009
Age based scheduling for asymmetric multiprocessors.
Proceedings of the ACM/IEEE Conference on High Performance Computing, 2009


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