Jaejin Park

According to our database, Jaejin Park authored at least 19 papers between 1994 and 2017.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2017

A 0.015-mm² Inductorless 32-GHz Clock Generator With Wide Frequency-Tuning Range in 28-nm CMOS Technology.

Gyu-Seob Jeong, Wooseok Kim, Jaejin Park, Taeik Kim, Hojin Park, Deog-Kyoon Jeong

IEEE Trans. Circuits Syst. II Express Briefs, 2017

2016

Session 12 overview: Efficient Power Conversion.

Vadim Ivanov, Jaejin Park

Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016

2014

Layout Synthesis and Loop Parameter Optimization of a Low-Jitter All-Digital Pixel Clock Generator.

Wooseok Kim, Jaejin Park, Hojin Park, Deog-Kyoon Jeong

IEEE J. Solid State Circuits, 2014

15.2 A 0.012mm² 3.1mW bang-bang digital fractional-N PLL with a power-supply-noise cancellation technique and a walking-one-phase-selection fractional frequency divider.

Jenlung Liu, Tae-Kwang Jang, Yonghee Lee, Jungeun Shin, Seunghoon Lee, Taeik Kim, Jaejin Park, Hojin Park

Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014

2013

A 0.032mm² 3.1mW synthesized pixel clock generator with 30psrms integrated jitter and 10-to-630MHz DCO tuning range.

Wooseok Kim, Jaejin Park, Jihyun F. Kim, Taeik Kim, Hojin Park, Deog-Kyoon Jeong

Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013

A 0.026mm² 5.3mW 32-to-2000MHz digital fractional-N phase locked-loop using a phase-interpolating phase-to-digital converter.

Tae-Kwang Jang, Nan Xing, Frank Liu, Jungeun Shin, Hyungreal Ryu, Jihyun F. Kim, Taeik Kim, Jaejin Park, Hojin Park

Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013

Verifying start-up failures in coupled ring oscillators in presence of variability using predictive global optimization.

Taehwan Kim, Do-Gyoon Song, Sangho Youn, Jaejin Park, Hojin Park, Jaeha Kim

Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2013

2012

An all-digital clock generator using a fractionally injection-locked oscillator in 65nm CMOS.

Pyoungwon Park, Jaejin Park, Hojin Park, SeongHwan Cho

Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012

A 0.004mm² 250μW ΔΣ TDC with time-difference accumulator and a 0.012mm² 2.5mW bang-bang digital PLL using PRNG for low-power SoC applications.

Jong-Phil Hong, Sung-Jin Kim, Jenlung Liu, Nan Xing, Tae-Kwang Jang, Jaejin Park, Jihyun F. Kim, Taeik Kim, Hojin Park

Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012

2011

A 0.8V, sub-mW, varactor-tuning ring-oscillator-based clock generator in 32nm CMOS.

Jenlung Liu, Sehyung Jeon, Tae-Kwang Jang, Dohyung Kim, Jihyun F. Kim, Jaejin Park, Hojin Park

Proceedings of the IEEE Asian Solid-State Circuits Conference, 2011

2008

CFGP: a web-based, comparative fungal genomics platform.

Jongsun Park, Bongsoo Park, Kyongyong Jung, Suwang Jang, Kwangyul Yu, Jaeyoung Choi, Sunghyung Kong, Jaejin Park, Seryun Kim, Hyojeong Kim, Soonok Kim, Jihyun F. Kim, Jaime E. Blair, Kwangwon Lee, Seogchan Kang, Yong-Hwan Lee

Nucleic Acids Res., 2008

FTFD: an informatics pipeline supporting phylogenomic analysis of fungal transcription factors.

Jongsun Park, Jaejin Park, Suwang Jang, Seryun Kim, Sunghyung Kong, Jaeyoung Choi, Kyohun Ahn, Juhyeon Kim, Seungmin Lee, Sunggon Kim, Bongsoo Park, Kyongyong Jung, Soonok Kim, Seogchan Kang, Yong-Hwan Lee

Bioinform., 2008

2007

A 1-V, 1.4-2.5 GHz Charge-Pump-Less PLL for a Phase Interpolator Based CDR.

Jaejin Park, J. F. Liu, L. Richard Carley, C. Patrick Yue

Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, 2007

2005

A low-power, 20-Gb/s continuous-time adaptive passive equalizer.

Ruifeng Sun, Jaejin Park, Frank O'Mahony, C. Patrick Yue

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

A 10-Gbps, 8-PAM parallel interface with crosstalk cancellation for future hard disk drive channel ICs.

Jaejin Park, Ruifeng Sun, L. Rick Carley, C. Patrick Yue

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

2000

A 1 mW 10-bit 500KSPS SAR A/D converter.

Jaejin Park, Ho-Jin Park, Jae-Whui Kim, Sangnam Seo, Philip Chung

Proceedings of the IEEE International Symposium on Circuits and Systems, 2000

1999

A 5-MHz IF digital FM demodulator.

Jaejin Park, Eurho Joe, Myung-Jun Choe, Bang-Sup Song

IEEE J. Solid State Circuits, 1999

1995

A single chip iΔ-Σ ADC with a built-in variable gain stage and DAC with a charge integrating subconverter for a 5 V 9600-b/s modem.

Daejeong Kim, Jaejin Park, Sungjoon Kim, Deog-Kyoon Jeong, Wonchan Kim

IEEE J. Solid State Circuits, August, 1995

1994

A Multibit Delta-Sigma D/A Converter Using a Charge Integrating Sub-Converter.

Daejong Kim, Jaejin Park, Sungjoon Kim, Deog-Kyoon Jeong, Wonchan Kim

Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994