Jaehyun Park

Orcid: 0000-0001-9205-8266

Affiliations:

Yonsei University, School of Electrical and Electronics Engineering, Seoul, Korea
Kwangwoon University, Department of Electronic Engineering, Seoul, Korea

According to our database¹, Jaehyun Park authored at least 3 papers between 2023 and 2024.

Collaborative distances:

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2024

Post-Layout Parasitic Capacitance Prediction Methodology Using Bayesian Optimization.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Electronics, Information, and Communication, 2024

2023

Cross-Coupled nFET Preamplifier for Low Voltage SRAM.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, September, 2023

Voltage Boosted Fail Detecting Circuit for Selective Write Assist and Cell Current Boosting for High-Density Low-Power SRAM.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., February, 2023