Jaehyeong Sim
Orcid: 0000-0001-8722-8486
According to our database1,
Jaehyeong Sim
authored at least 28 papers
between 2012 and 2024.
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Bibliography
2024
Q-LAtte: An Efficient and Versatile LSTM Model for Quantized Attention-Based Time Series Forecasting in Building Energy Applications.
IEEE Access, 2024
IEEE Access, 2024
AlphaAccelerator: An Automatic Neural FPGA Accelerator Design Framework Based on GNNs.
Proceedings of the 21st International SoC Design Conference, 2024
BS2: Bit-Serial Architecture Exploiting Weight Bit Sparsity for Efficient Deep Learning Acceleration.
Proceedings of the 21st International SoC Design Conference, 2024
Proceedings of the 21st International SoC Design Conference, 2024
Proceedings of the International Conference on Communications, 2024
Proceedings of the International Conference on Communications, 2024
2023
Proceedings of the 20th International SoC Design Conference, 2023
Proceedings of the International Conference on Communications, 2023
2022
S-FLASH: A NAND Flash-Based Deep Neural Network Accelerator Exploiting Bit-Level Sparsity.
IEEE Trans. Computers, 2022
2020
An Energy-Efficient Deep Convolutional Neural Network Inference Processor With Enhanced Output Stationary Dataflow in 65-nm CMOS.
IEEE Trans. Very Large Scale Integr. Syst., 2020
IEEE Trans. Circuits Syst., 2020
An Energy-Efficient Deep Convolutional Neural Network Training Accelerator for In Situ Personalization on Smart Devices.
IEEE J. Solid State Circuits, 2020
2019
A PVT-robust Customized 4T Embedded DRAM Cell Array for Accelerating Binary Neural Networks.
Proceedings of the International Conference on Computer-Aided Design, 2019
An Energy-efficient Processing-in-memory Architecture for Long Short Term Memory in Spin Orbit Torque MRAM.
Proceedings of the International Conference on Computer-Aided Design, 2019
eSRCNN: A Framework for Optimizing Super-Resolution Tasks on Diverse Embedded CNN Accelerators.
Proceedings of the International Conference on Computer-Aided Design, 2019
NAND-Net: Minimizing Computational Complexity of In-Memory Processing for Binary Neural Networks.
Proceedings of the 25th IEEE International Symposium on High Performance Computer Architecture, 2019
A 47.4µJ/epoch Trainable Deep Convolutional Neural Network Accelerator for In-Situ Personalization on Smart Devices.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2019
2018
TrainWare: A Memory Optimized Weight Update Architecture for On-Device Convolutional Neural Network Training.
Proceedings of the International Symposium on Low Power Electronics and Design, 2018
Proceedings of the International Conference on Computer-Aided Design, 2018
2017
IEEE Trans. Circuits Syst. II Express Briefs, 2017
Proceedings of the 2017 IEEE/ACM International Symposium on Low Power Electronics and Design, 2017
Proceedings of the 54th Annual Design Automation Conference, 2017
2016
A 5-Gb/s 2.67-mW/Gb/s Digital Clock and Data Recovery With Hybrid Dithering Using a Time-Dithered Delta-Sigma Modulator.
IEEE Trans. Very Large Scale Integr. Syst., 2016
14.6 A 1.42TOPS/W deep convolutional neural network recognition processor for intelligent IoE systems.
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016
2014
Proceedings of the 32nd IEEE International Conference on Computer Design, 2014
2013
PowerField: A Probabilistic Approach for Temperature-to-Power Conversion Based on Markov Random Field Theory.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013
2012
PowerField: a transient temperature-to-power technique based on Markov random field theory.
Proceedings of the 49th Annual Design Automation Conference 2012, 2012