Jaehwan Jung

According to our database, Jaehwan Jung authored at least 12 papers between 2013 and 2019.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2019

Energy-Efficient Symmetric BC-BCH Decoder Architecture for Mobile Storages.

Seokha Hwang, Seungsik Moon, Jaehwan Jung, Daesung Kim, In-Cheol Park, Jeongseok Ha, Youngjoo Lee

IEEE Trans. Circuits Syst. I Regul. Pap., 2019

2018

Interference Cancellation Architecture for Pipelined Parallel MIMO Detectors.

Byeong Yong Kong, Jaehwan Jung, In-Cheol Park

Proceedings of the 25th IEEE International Conference on Electronics, Circuits and Systems, 2018

A 2.4pJ/bit, 6.37Gb/s SPC-enhanced BC-BCH decoder in 65nm CMOS for NAND flash storage systems.

Jaehwan Jung, In-Cheol Park, Youngjoo Lee

Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018

2017

Multi-Bit Flipping Decoding of LDPC Codes for NAND Storage Systems.

Jaehwan Jung, In-Cheol Park

IEEE Commun. Lett., 2017

An energy-optimized (37840, 34320) symmetric BC-BCH decoder for healthy mobile storages.

Seokha Hwang, Jaehwan Jung, Daesung Kim, Jeongseok Ha, In-Cheol Park, Youngjoo Lee

Proceedings of the IEEE Asian Solid-State Circuits Conference, 2017

2016

Area-Efficient Approach for Generating Quantized Gaussian Noise.

Jaejoon Choi, Jaehwan Jung, In-Cheol Park

IEEE Trans. Circuits Syst. I Regul. Pap., 2016

Energy-Scalable 4KB LDPC Decoding Architecture for NAND-Flash-Based Storage Systems.

Youngjoo Lee, Jaehwan Jung, In-Cheol Park

IEICE Trans. Electron., 2016

2015

Low-Complexity Tree Architecture for Finding the First Two Minima.

Youngjoo Lee, Bongjin Kim, Jaehwan Jung, In-Cheol Park

IEEE Trans. Circuits Syst. II Express Briefs, 2015

Efficient Parallel Architecture for Linear Feedback Shift Registers.

Jaehwan Jung, Hoyoung Yoo, Youngjoo Lee, In-Cheol Park

IEEE Trans. Circuits Syst. II Express Briefs, 2015

Unidirectional ring ethernet for low-complexity in-vehicle control network.

Injae Yoo, Mina Hwang, Jaehwan Jung, Suhyun Kim, In-Cheol Park

Proceedings of the IEEE International Conference on Industrial Technology, 2015

2013

Area-Efficient Multimode Encoding Architecture for Long BCH Codes.

Hoyoung Yoo, Jaehwan Jung, Jihyuck Jo, In-Cheol Park

IEEE Trans. Circuits Syst. II Express Briefs, 2013

A 2.74-pJ/bit, 17.7-Gb/s Iterative Concatenated-BCH Decoder in 65-nm CMOS for NAND Flash Memory.

Youngjoo Lee, Hoyoung Yoo, Jaehwan Jung, Jihyuck Jo, In-Cheol Park

IEEE J. Solid State Circuits, 2013