Jaehoon Yu

Orcid: 0000-0001-6639-7694

According to our database1, Jaehoon Yu authored at least 55 papers between 2005 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2024
The Breakthrough Memory Solutions for Improved Performance on LLM Inference.
IEEE Micro, 2024

Pianissimo: A Sub-mW Class DNN Accelerator With Progressively Adjustable Bit-Precision.
IEEE Access, 2024

Toward Improving Ensemble-Based Collaborative Inference at the Edge.
IEEE Access, 2024

Exploration of Hyperdimensional Computing Using Locality-Sensitive Hashing Mechanism on FPGA.
Proceedings of the IEEE International Conference on Consumer Electronics, 2024

2023
A Fully-Parallel Annealing Algorithm with Autonomous Pinning Effect Control for Various Combinatorial Optimization Problems.
IEICE Trans. Inf. Syst., December, 2023

TT-MLP: Tensor Train Decomposition on Deep MLPs.
IEEE Access, 2023

Recurrent Residual Networks Contain Stronger Lottery Tickets.
IEEE Access, 2023

Pianissimo: A Sub-mW Class DNN Accelerator with Progressive Bit-by-Bit Datapath Architecture for Adaptive Inference at Edge.
Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023

A Highly Accurate and Parallel Vision MLP FPGA Accelerator based on FP7/8 SIMD Operations.
Proceedings of the 16th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2023

Amorphica: 4-Replica 512 Fully Connected Spin 336MHz Metamorphic Annealer with Programmable Optimization Strategy and Compressed-Spin-Transfer Multi-Chip Extension.
Proceedings of the IEEE International Solid- State Circuits Conference, 2023

Samsung PIM/PNM for Transfmer Based AI : Energy Efficiency on PIM/PNM Cluster.
Proceedings of the 35th IEEE Hot Chips Symposium, 2023

Decision Forest Training Accelerator Based on Binary Feature Decomposition.
Proceedings of the 31st IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2023

Flexibly Controllable Dynamic Cooling Methods for Solid-State Annealing Processors to Improve Combinatorial Optimization Performance.
Proceedings of the IEEE Symposium in Low-Power and High-Speed Chips, 2023

2022
A Hybrid Integer Encoding Method for Obtaining High-Quality Solutions of Quadratic Knapsack Problems on Solid-State Annealers.
IEICE Trans. Inf. Syst., December, 2022

Investigating Small Device Implementation of FRET-based Optical Reservoir Computing.
Proceedings of the 65th IEEE International Midwest Symposium on Circuits and Systems, 2022

Hiddenite: 4K-PE Hidden Network Inference 4D-Tensor Engine Exploiting On-Chip Model Construction Achieving 34.8-to-16.0TOPS/W for CIFAR-100 and ImageNet.
Proceedings of the IEEE International Solid-State Circuits Conference, 2022

APC-SCA: A Fully-Parallel Annealing Algorithm with Autonomous Pinning Effect Control.
Proceedings of the IEEE International Parallel and Distributed Processing Symposium, 2022

Multicoated Supermasks Enhance Hidden Networks.
Proceedings of the International Conference on Machine Learning, 2022

2021
ProgressiveNN: Achieving Computational Scalability with Dynamic Bit-Precision Adjustment by MSB-first Accumulative Computation.
Int. J. Netw. Comput., 2021

ExtraFerns: Fully Parallel Ensemble Learning Technique with Random Projection and Non-Greedy yet Minimal Memory Access Training.
Int. J. Netw. Comput., 2021

Selective Fine-Tuning on a Classifier Ensemble: Realizing Adaptive Neural Networks With a Diversified Multi-Exit Architecture.
IEEE Access, 2021

Edge Inference Engine for Deep & Random Sparse Neural Networks with 4-bit Cartesian-Product MAC Array and Pipelined Activation Aligner.
Proceedings of the IEEE Hot Chips 33 Symposium, 2021

A High-Performance and Flexible FPGA Inference Accelerator for Decision Forests Based on Prior Feature Space Partitioning.
Proceedings of the International Conference on Field-Programmable Technology, 2021

MUX Granularity Oriented Iterative Technology Mapping for Implementing Compute-Intensive Applications on Via-Switch FPGA.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

Hidden-Fold Networks: Random Recurrent Residuals Using Sparse Supermasks.
Proceedings of the 32nd British Machine Vision Conference 2021, 2021

2020
Sneak Path Free Reconfiguration With Minimized Programming Steps for Via-Switch Crossbar-Based FPGA.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

Logarithm-approximate floating-point multiplier is applicable to power-efficient neural network training.
Integr., 2020

33.3 Via-Switch FPGA: 65nm CMOS Implementation and Architecture Extension for Al Applications.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020

Low-Cost Reservoir Computing using Cellular Automata and Random Forests.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

ProgressiveNN: Achieving Computational Scalability without Network Alteration by MSB-first Accumulative Computation.
Proceedings of the Eighth International Symposium on Computing and Networking, 2020

ExtraFerns: Fully Parallel Ensemble Learning Technique with Non-Greedy yet Minimal Memory Access Training.
Proceedings of the Eighth International Symposium on Computing and Networking, 2020

Memory Efficient Training using Lookup-Table-based Quantization for Neural Network.
Proceedings of the 2nd IEEE International Conference on Artificial Intelligence Circuits and Systems, 2020

2019
Parallelism-flexible Convolution Core for Sparse Convolutional Neural Networks on FPGA.
IPSJ Trans. Syst. LSI Des. Methodol., 2019

Minimizing Power for Neural Network Training with Logarithm-Approximate Floating-Point Multiplier.
Proceedings of the 29th International Symposium on Power and Timing Modeling, 2019

Training Data Reduction using Support Vectors for Neural Networks.
Proceedings of the 2019 Asia-Pacific Signal and Information Processing Association Annual Summit and Conference, 2019

Distilling Knowledge for Non-Neural Networks.
Proceedings of the 2019 Asia-Pacific Signal and Information Processing Association Annual Summit and Conference, 2019

2018
Via-Switch FPGA: Highly Dense Mixed-Grained Reconfigurable Architecture With Overlay Via-Switch Crossbars.
IEEE Trans. Very Large Scale Integr. Syst., 2018

Phase Locking Value Calculator Based on Hardware-Oriented Mathematical Expression.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2018

Hardware Architecture for High-Speed Object Detection Using Decision Tree Ensemble.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2018

Decomposed Vector Histograms of Oriented Gradients for Efficient Hardware Implementation.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2018

Interconnect Delay Analysis for RRAM Crossbar Based FPGA.
Proceedings of the 2018 IEEE Computer Society Annual Symposium on VLSI, 2018

Sneak path free reconfiguration of via-switch crossbars based FPGA.
Proceedings of the International Conference on Computer-Aided Design, 2018

Hardware Architecture for Fast General Object Detection using Aggregated Channel Features.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2018

2017
A Low-Energy Application Specific Instruction-Set Processor towards a Low-Computational Lossless Compression Method for Stimuli Position Data of Artificial Vision Systems.
J. Inf. Process., 2017

Deformable Part Model Based Arrhythmia Detection Using Time Domain Features.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2017

Hardware-oriented algorithm for phase synchronization analysis of biomedical signals.
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2017

2016
A programmable controller for spatio-temporal pattern stimulation of cortical visual prosthesis.
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2016

2015
Design of generic hardware for soft cascade-based linear SVM classification.
Proceedings of the 2015 International Symposium on Intelligent Signal Processing and Communication Systems, 2015

A low-energy ASIP with flexible exponential Golomb codec for lossless data compression toward artificial vision systems.
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2015

2014
Corrections to "A Speed-Up Scheme Based on Multiple-Instance Pruning for Pedestrian Detection Using a Support Vector Machine".
IEEE Trans. Image Process., 2014

Normalized channel features for accurate pedestrian detection.
Proceedings of the 6th International Symposium on Communications, 2014

An efficient data compression method for artificial vision systems and its low energy implementation using ASIP technology.
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2014

2013
A Speed-Up Scheme Based on Multiple-Instance Pruning for Pedestrian Detection Using a Support Vector Machine.
IEEE Trans. Image Process., 2013

2007
Implementation of AV Streaming System Using Peer-to-Peer Communication.
Proceedings of the 4th IEEE Consumer Communications and Networking Conference, 2007

2005
Performance of an Operating High Energy Physics Data Grid: DØSAR-Grid
CoRR, 2005


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