Jaehong Jung
Orcid: 0000-0003-3690-4901
According to our database1,
Jaehong Jung
authored at least 19 papers
between 2016 and 2024.
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Bibliography
2024
A Fully Integrated, Low-Noise, Cost-Effective Single-Crystal-Oscillator-Based Clock Management IC in 28-nm CMOS.
IEEE J. Solid State Circuits, June, 2024
Tactile Speech Communication: Reception of Words and Two-Way Messages through a Phoneme-Based Display.
Virtual Worlds, 2024
2023
A 208-MHz, 0.75-mW Self-Calibrated Reference Frequency Quadrupler for a 2-GHz Fractional-N Ring-PLL in 4-nm FinFET CMOS.
IEEE Trans. Circuits Syst. II Express Briefs, August, 2023
A 2.4-to-4.2GHz 440.2fsrms-Integrated-Jitter 4.3mW Ring-Oscillator-Based PLL Using a Switched-Capacitor-Bias-Based Sampling PD in 4nm FinFET CMOS.
Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023
A Wide Frequency Range, Small Area and Low Supply Memory Interface PLL Using a Process and Temperature Variation Aware Current Reference in 3 nm Gate-All Around CMOS.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2023
2022
A Single-Crystal-Oscillator-Based Clock-Management IC with 18× Start-Up Time Reduction and 0.68ppm/ºC Duty-Cycled Machine-Learning-Based RCO Calibration.
Proceedings of the IEEE International Solid-State Circuits Conference, 2022
A 52MHz -158.2dBc/Hz PN @ 100kHz Digitally Controlled Crystal Oscillator Utilizing a Capacitive-Load-Dependent Dynamic Feedback Resistor in 28nm CMOS.
Proceedings of the IEEE International Solid-State Circuits Conference, 2022
2020
IEEE Trans. Haptics, 2020
A 4GHz 0.73psrms-Integrated-Jitter PVT-Insensitive Fractional-N Sub-Sampling Ring PLL with a Jitter-Tracking DLL-Assisted DTC.
Proceedings of the IEEE Symposium on VLSI Circuits, 2020
An RF Transceiver with Full Digital Interface Supporting 5G New Radio FR1 with 3.84Gbps DL/1.92Gbps UL and Dual-Band GNSS in 14nm FinFET CMOS.
Proceedings of the IEEE Symposium on VLSI Circuits, 2020
2019
A Blocker-Tolerant Direct Sampling Receiver for Wireless Multi-Channel Communication in 14nm FinFET CMOS.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2019
A 9.4MHz-to-2.4GHz Jitter-Power Reconfigurable Fractional-N Ring PLL for Multi-Standard Applications in 7nm FinFET CMOS Technology.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2019
2018
A 1.08-nW/kHz 13.2-ppm/°C Self-Biased Timer Using Temperature-Insensitive Resistive Current.
IEEE J. Solid State Circuits, 2018
A 0.75-3.0-Gb/s Dual-Mode Temperature-Tolerant Referenceless CDR With a Deadzone-Compensated Frequency Detector.
IEEE J. Solid State Circuits, 2018
Speech Communication Through the Skin: Design of Learning Protocols and Initial Findings.
Proceedings of the Design, User Experience, and Usability: Designing Interactions, 2018
A Comparative Study of Phoneme- and Word-Based Learning of English Words Presented to the Skin.
Proceedings of the Haptics: Science, Technology, and Applications, 2018
2017
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017
2016
IEEE Trans. Multim., 2016