Jaegeun Song

Orcid: 0000-0002-9327-9973

According to our database1, Jaegeun Song authored at least 10 papers between 2018 and 2024.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

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In proceedings 
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PhD thesis 
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Links

On csauthors.net:

Bibliography

2024
A 4-nm 1.15 TB/s HBM3 Interface With Resistor-Tuned Offset Calibration and In Situ Margin Detection.
IEEE J. Solid State Circuits, January, 2024

2023
A 4nm 1.15TB/s HBM3 Interface with Resistor-Tuned Offset-Calibration and In-Situ Margin-Detection.
Proceedings of the IEEE International Solid- State Circuits Conference, 2023

2022
A 9-bit 500-MS/s 2-bit/cycle SAR ADC With Error-Tolerant Interpolation Technique.
IEEE J. Solid State Circuits, 2022

An 88.9-dB SNR Fully-Dynamic Noise-Shaping SAR Capacitance-to-Digital Converter.
IEEE J. Solid State Circuits, 2022

Home IoT device management blockchain platform using smart contracts and a countermeasure against 51% attacks.
Proceedings of the APIT 2022: 4th Asia Pacific Information Technology Conference, Virtual Event, Thailand, January 14, 2022

2021
A Capacitively Coupled CT Δ ΣM With Chopping Artifacts Rejection for Sensor Readout ICs.
IEEE Trans. Circuits Syst. I Regul. Pap., 2021

2020
A 0.5 V 10-bit 3 MS/s SAR ADC With Adaptive-Reset Switching Scheme and Near-Threshold Voltage-Optimized Design Technique.
IEEE Trans. Circuits Syst. II Express Briefs, 2020

An 11-b 100-MS/s Fully Dynamic Pipelined ADC Using a High-Linearity Dynamic Amplifier.
IEEE J. Solid State Circuits, 2020

A 1 MS/s 9.15 ENOB Low-Power SAR ADC with Triple-Charge-Sharing Technique.
Proceedings of the International SoC Design Conference, 2020

2018
A Near-Threshold Voltage Oriented Digital Cell Library for High-Energy Efficiency and Optimized Performance in 65nm CMOS Process.
IEEE Trans. Circuits Syst. I Regul. Pap., 2018


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