Jae-Won Nam

Orcid: 0000-0003-0986-4107

According to our database1, Jae-Won Nam authored at least 23 papers between 2009 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Links

On csauthors.net:

Bibliography

2023
High-Speed Light Detection Sensor for Hardware Security in Standard CMOS Technology.
IEEE Trans. Circuits Syst. II Express Briefs, October, 2023

Optimizing EV Chargers Location via Integer Programming.
CoRR, 2023

Analysis of Quarter Method Applied ROM-Based DDFS Architecture.
IEEE Access, 2023

AMS Circuit Design Optimization Technique Based on ANN Regression Model With VAE Structure.
IEEE Access, 2023

Regression Model-based VCO Design Optimization Technique.
Proceedings of the International Conference on Electronics, Information, and Communication, 2023

2022
A Low-Power Class-C Voltage-Controlled Oscillator With Robust Start-Up and Compact High-Q Capacitor Array.
IEEE Trans. Circuits Syst. II Express Briefs, 2022

Compact SRAM-Based PUF Chip Employing Body Voltage Control Technique.
IEEE Access, 2022

2021
Machine-Learning based Analog and Mixed-signal Circuit Design and Optimization.
Proceedings of the International Conference on Information Networking, 2021

Generative Adversarial Attacks on Fingerprint Recognition Systems.
Proceedings of the International Conference on Information Networking, 2021

HW-BCP: A Custom Hardware Accelerator for SAT Suitable for Single Chip Implementation for Large Benchmarks.
Proceedings of the ASPDAC '21: 26th Asia and South Pacific Design Automation Conference, 2021

2020
A 12.8-Gbaud ADC-Based Wireline Receiver With Embedded IIR Equalizer.
IEEE J. Solid State Circuits, 2020

2019
A 12.8-Gbaud ADC-based NRZ/PAM4 Receiver with Embedded Tunable IIR Equalization Filter Achieving 2.43-pJ/b in 65nm CMOS.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2019

2018
A 12-Bit 1.6, 3.2, and 6.4 GS/s 4-b/Cycle Time-Interleaved SAR ADC With Dual Reference Shifting and Interpolation.
IEEE J. Solid State Circuits, 2018

2016
An Embedded Passive Gain Technique for Asynchronous SAR ADC Achieving 10.2 ENOB 1.36-mW at 95-MS/s in 65 nm CMOS.
IEEE Trans. Circuits Syst. I Regul. Pap., 2016

A 12-bit 1.6 GS/s interleaved SAR ADC with dual reference shifting and interpolation achieving 17.8 fJ/conv-step in 65nm CMOS.
Proceedings of the 2016 IEEE Symposium on VLSI Circuits, 2016

2013
A 95-MS/s 11-bit 1.36-mW asynchronous SAR ADC with embedded passive gain in 65nm CMOS.
Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 2013

2012
A Dual-Channel Pipelined ADC With Sub-ADC Based on Flash-SAR Architecture.
IEEE Trans. Circuits Syst. II Express Briefs, 2012

2011
A 12-bit 200-MS/s pipelined A/D converter with sampling skew reduction technique.
Microelectron. J., 2011

A 10-bit 30-MS/s successive approximation register analog-to-digital converter for low-power sub-sampling applications.
Microelectron. J., 2011

A 12-bit 100-MS/s pipelined ADC in 45-nm CMOS.
Proceedings of the International SoC Design Conference, 2011

2010
A 9-bit 80 MS/s Successive Approximation Register Analog-to-Digital Converter With a Capacitor Reduction Technique.
IEEE Trans. Circuits Syst. II Express Briefs, 2010

A 9.15mW 0.22mm<sup>2</sup> 10b 204MS/s pipelined SAR ADC in 65nm CMOS.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2010

2009
A 2.85mW 0.12mm2 1.0V 11-bit 20-MS/s algorithmic ADC in 65nm CMOS.
Proceedings of the 35th European Solid-State Circuits Conference, 2009


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