Jae-Won Nam
Orcid: 0000-0003-0986-4107
According to our database1,
Jae-Won Nam
authored at least 24 papers
between 2009 and 2024.
Collaborative distances:
Collaborative distances:
Timeline
Legend:
Book In proceedings Article PhD thesis Dataset OtherLinks
On csauthors.net:
Bibliography
2024
A 4.3 GS/s Time-Interleaved ΔΣ DAC With Temperature-Insensitive Bias and Harmonic Cancellation for Qubit Control.
IEEE Trans. Circuits Syst. II Express Briefs, November, 2024
2023
IEEE Trans. Circuits Syst. II Express Briefs, October, 2023
AMS Circuit Design Optimization Technique Based on ANN Regression Model With VAE Structure.
IEEE Access, 2023
Proceedings of the International Conference on Electronics, Information, and Communication, 2023
2022
A Low-Power Class-C Voltage-Controlled Oscillator With Robust Start-Up and Compact High-Q Capacitor Array.
IEEE Trans. Circuits Syst. II Express Briefs, 2022
IEEE Access, 2022
2021
Proceedings of the International Conference on Information Networking, 2021
Proceedings of the International Conference on Information Networking, 2021
HW-BCP: A Custom Hardware Accelerator for SAT Suitable for Single Chip Implementation for Large Benchmarks.
Proceedings of the ASPDAC '21: 26th Asia and South Pacific Design Automation Conference, 2021
2020
IEEE J. Solid State Circuits, 2020
2019
A 12.8-Gbaud ADC-based NRZ/PAM4 Receiver with Embedded Tunable IIR Equalization Filter Achieving 2.43-pJ/b in 65nm CMOS.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2019
2018
A 12-Bit 1.6, 3.2, and 6.4 GS/s 4-b/Cycle Time-Interleaved SAR ADC With Dual Reference Shifting and Interpolation.
IEEE J. Solid State Circuits, 2018
2016
An Embedded Passive Gain Technique for Asynchronous SAR ADC Achieving 10.2 ENOB 1.36-mW at 95-MS/s in 65 nm CMOS.
IEEE Trans. Circuits Syst. I Regul. Pap., 2016
A 12-bit 1.6 GS/s interleaved SAR ADC with dual reference shifting and interpolation achieving 17.8 fJ/conv-step in 65nm CMOS.
Proceedings of the 2016 IEEE Symposium on VLSI Circuits, 2016
2013
A 95-MS/s 11-bit 1.36-mW asynchronous SAR ADC with embedded passive gain in 65nm CMOS.
Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 2013
2012
IEEE Trans. Circuits Syst. II Express Briefs, 2012
2011
Microelectron. J., 2011
A 10-bit 30-MS/s successive approximation register analog-to-digital converter for low-power sub-sampling applications.
Microelectron. J., 2011
Proceedings of the International SoC Design Conference, 2011
2010
A 9-bit 80 MS/s Successive Approximation Register Analog-to-Digital Converter With a Capacitor Reduction Technique.
IEEE Trans. Circuits Syst. II Express Briefs, 2010
Proceedings of the IEEE Custom Integrated Circuits Conference, 2010
2009
Proceedings of the 35th European Solid-State Circuits Conference, 2009