Jae-sun Seo
Orcid: 0000-0002-4551-7789
According to our database1,
Jae-sun Seo
authored at least 174 papers
between 2007 and 2024.
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Bibliography
2024
IEEE J. Solid State Circuits, July, 2024
MACC-SRAM: A Multistep Accumulation Capacitor-Coupling In-Memory Computing SRAM Macro for Deep Convolutional Neural Networks.
IEEE J. Solid State Circuits, June, 2024
ACM Trans. Reconfigurable Technol. Syst., March, 2024
Guest Editorial Introduction to the Special Section on the 2023 IEEE International Solid-State Circuits Conference (ISSCC).
IEEE J. Solid State Circuits, January, 2024
A Fully Digital and Row-Pipelined Compute-in-Memory Neural Network Accelerator With System-on-Chip-Level Benchmarking for Augmented/Virtual Reality Applications.
IEEE Micro, 2024
CoRR, 2024
CoRR, 2024
Proceedings of the IEEE/CVF Winter Conference on Applications of Computer Vision, 2024
Torch2Chip: An End-to-end Customizable Deep Neural Network Compression and Deployment Toolkit for Prototype Hardware Accelerator Design.
Proceedings of the Seventh Annual Conference on Machine Learning and Systems, 2024
Proceedings of the 57th IEEE/ACM International Symposium on Microarchitecture, 2024
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2024
Proceedings of the 29th ACM/IEEE International Symposium on Low Power Electronics and Design, 2024
3D IC Architecture Evaluation and Optimization with Digital Compute-in-Memory Designs.
Proceedings of the 29th ACM/IEEE International Symposium on Low Power Electronics and Design, 2024
Spiking Neural Network with Learnable Threshold for Event-based Classification and Object Detection.
Proceedings of the International Joint Conference on Neural Networks, 2024
IM-SNN: Memory-Efficient Spiking Neural Network with Low-Precision Membrane Potentials and Weights.
Proceedings of the International Conference on Neuromorphic Systems, 2024
Proceedings of the Computer Vision - ECCV 2024, 2024
SP-IMC: A Sparsity Aware In-Memory-Computing Macro in 28nm CMOS with Configurable Sparse Representation for Highly Sparse DNN Workloads.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2024
Proceedings of the 29th Asia and South Pacific Design Automation Conference, 2024
Proceedings of the Thirty-Eighth AAAI Conference on Artificial Intelligence, 2024
2023
Algorithm-hardware Co-optimization for Energy-efficient Drone Detection on Resource-constrained FPGA.
ACM Trans. Reconfigurable Technol. Syst., June, 2023
PIMCA: A Programmable In-Memory Computing Accelerator for Energy-Efficient DNN Inference.
IEEE J. Solid State Circuits, May, 2023
A 28-nm 8-bit Floating-Point Tensor Core-Based Programmable CNN Training Processor With Dynamic Structured Sparsity.
IEEE J. Solid State Circuits, 2023
NeuroBench: Advancing Neuromorphic Computing through Collaborative, Fair and Representative Benchmarking.
CoRR, 2023
Slimmed Asymmetrical Contrastive Learning and Cross Distillation for Lightweight Model Training.
Proceedings of the Advances in Neural Information Processing Systems 36: Annual Conference on Neural Information Processing Systems 2023, 2023
Improving the Efficiency of CMOS Image Sensors through In-Sensor Selective Attention.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023
Proceedings of the 49th IEEE European Solid State Circuits Conference, 2023
Proceedings of the 49th IEEE European Solid State Circuits Conference, 2023
A Time-Memory-based CMOS Vision Sensor with In-Pixel Temporal Derivative Computing for Multi-Mode Image Processing.
Proceedings of the 49th IEEE European Solid State Circuits Conference, 2023
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023
PRIVE: Efficient RRAM Programming with Chip Verification for RRAM-based In-Memory Computing Acceleration.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023
Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023
A 92 F<sup>2</sup> / bit Physically Unclonable Function Exploiting Channel Charge Injection and Mismatch Accumulation.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2023
A 138-TOPS/W Delta-Sigma Modulator-Based Variable- Resolution Activation in-Memory Computing Macro.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2023
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2023
3D-ISC: A 65nm 3D Compatible In-Sensor Computing Accelerator with Reconfigurable Tile Architecture for Real-Time DVS Data Compression.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2023
Proceedings of the 15th IEEE International Conference on ASIC, 2023
2022
Neuromorph. Comput. Eng., December, 2022
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022
IEEE Micro, 2022
ACM J. Emerg. Technol. Comput. Syst., 2022
IEEE Des. Test, 2022
Proceedings of the Advances in Neural Information Processing Systems 35: Annual Conference on Neural Information Processing Systems 2022, 2022
Proceedings of the IEEE International Reliability Physics Symposium, 2022
Big-Little Chiplets for In-Memory Acceleration of DNNs: A Scalable Heterogeneous Architecture.
Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design, 2022
A 28nm 8-bit Floating-Point Tensor Core based CNN Training Processor with Dynamic Activation/Weight Sparsification.
Proceedings of the 48th IEEE European Solid State Circuits Conference, 2022
Proceedings of the 48th IEEE European Solid State Circuits Conference, 2022
Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022
XMA: a crossbar-aware multi-task adaption framework via shift-based mask learning method.
Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022
Proceedings of the IEEE/CVF Conference on Computer Vision and Pattern Recognition, 2022
A 177 TOPS/W, Capacitor-based In-Memory Computing SRAM Macro with Stepwise-Charging/Discharging DACs and Sparsity-Optimized Bitcells for 4-Bit Deep Convolutional Neural Networks.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2022
XBM: A Crossbar Column-wise Binary Mask Learning Method for Efficient Multiple Task Adaption.
Proceedings of the 27th Asia and South Pacific Design Automation Conference, 2022
Spatial-temporal Data Compression of Dynamic Vision Sensor Output with High Pixel-level Saliency using Low-precision Sparse Autoencoder.
Proceedings of the 56th Asilomar Conference on Signals, Systems, and Computers, ACSSC 2022, Pacific Grove, CA, USA, October 31, 2022
2021
SIAM: Chiplet-based Scalable In-Memory Acceleration with Mesh for Deep Neural Networks.
ACM Trans. Embed. Comput. Syst., 2021
Structured Pruning of RRAM Crossbars for Efficient In-Memory Computing Acceleration of Deep Neural Networks.
IEEE Trans. Circuits Syst. II Express Briefs, 2021
An Energy-Efficient Deep Convolutional Neural Network Accelerator Featuring Conditional Computing and Low External Memory Access.
IEEE J. Solid State Circuits, 2021
Guest Editorial Cross-Layer Designs, Methodologies, and Systems to Enable Micro AI for On-Device Intelligence.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2021
A Survey on the Optimization of Neural Network Accelerators for Micro-AI On-Device Inference.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2021
RA-BNN: Constructing Robust & Accurate Binary Neural Network to Simultaneously Defend Adversarial Bit-Flip Attack and Improve Accuracy.
CoRR, 2021
PIMCA: A 3.4-Mb Programmable In-Memory Computing Accelerator in 28nm for On-Chip DNN Inference.
Proceedings of the 2021 Symposium on VLSI Circuits, Kyoto, Japan, June 13-19, 2021, 2021
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021
Proceedings of the IEEE International Reliability Physics Symposium, 2021
Characterization and Mitigation of Relaxation Effects on Multi-level RRAM based In-Memory Computing.
Proceedings of the IEEE International Reliability Physics Symposium, 2021
Algorithm-Hardware Co-Optimization for Energy-Efficient Drone Detection on Resource-Constrained FPGA.
Proceedings of the International Conference on Field-Programmable Technology, 2021
FixyFPGA: Efficient FPGA Accelerator for Deep Neural Networks with High Element-Wise Sparsity and without External Memory Access.
Proceedings of the 31st International Conference on Field-Programmable Logic and Applications, 2021
End-to-End FPGA-based Object Detection Using Pipelined CNN and Non-Maximum Suppression.
Proceedings of the 31st International Conference on Field-Programmable Logic and Applications, 2021
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021
Leveraging Noise and Aggressive Quantization of In-Memory Computing for Robust DNN Hardware Against Adversarial Input and Weight Attacks.
Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021
System-Level Benchmarking of Chiplet-based IMC Architectures for Deep Neural Network Acceleration.
Proceedings of the 14th IEEE International Conference on ASIC, 2021
2020
IEEE Trans. Very Large Scale Integr. Syst., 2020
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020
ECG Authentication Hardware Design With Low-Power Signal Processing and Neural Network Optimization With Low Precision and Structured Compression.
IEEE Trans. Biomed. Circuits Syst., 2020
IEEE J. Solid State Circuits, 2020
An 8.93 TOPS/W LSTM Recurrent Neural Network Accelerator Featuring Hierarchical Coarse-Grain Sparsity for On-Device Speech Recognition.
IEEE J. Solid State Circuits, 2020
C3SRAM: An In-Memory-Computing SRAM Macro Based on Robust Capacitive Coupling Computing Mechanism.
IEEE J. Solid State Circuits, 2020
A Smart Hardware Security Engine Combining Entropy Sources of ECG, HRV, and SRAM PUF for Authentication and Secret Key Generation.
IEEE J. Solid State Circuits, 2020
IEEE J. Emerg. Sel. Topics Circuits Syst., 2020
IEEE Des. Test, 2020
Regulation Control Design Techniques for Integrated Switched Capacitor Voltage Regulators.
Proceedings of the 63rd IEEE International Midwest Symposium on Circuits and Systems, 2020
Proceedings of the International SoC Design Conference, 2020
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020
Impact of Read Disturb on Multilevel RRAM based Inference Engine: Experiments and Model Prediction.
Proceedings of the 2020 IEEE International Reliability Physics Symposium, 2020
Proceedings of the 21st Annual Conference of the International Speech Communication Association, 2020
Proceedings of the 2020 International Joint Conference on Neural Networks, 2020
Proceedings of the Twenty-Ninth International Joint Conference on Artificial Intelligence, 2020
FPGA-based Low-Batch Training Accelerator for Modern CNNs Featuring High Bandwidth Memory.
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020
An On-Chip Learning Accelerator for Spiking Neural Networks using STT-RAM Crossbar Arrays.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020
Proceedings of the 2020 IEEE/CVF Conference on Computer Vision and Pattern Recognition, 2020
Deep Convolutional Neural Network Accelerator Featuring Conditional Computing and Low External Memory Access.
Proceedings of the 2020 IEEE Custom Integrated Circuits Conference, 2020
2019
A Real-Time 17-Scale Object Detection Accelerator With Adaptive 2000-Stage Classification in 65 nm CMOS.
IEEE Trans. Circuits Syst. I Regul. Pap., 2019
Monolithically Integrated RRAM- and CMOS-Based In-Memory Computing Optimizations for Efficient Deep Learning.
IEEE Micro, 2019
A 1.06- $\mu$ W Smart ECG Processor in 65-nm CMOS for Real-Time Biometric Authentication and Personal Cardiac Monitoring.
IEEE J. Solid State Circuits, 2019
Guest Editors' Introduction: Hardware and Algorithms for Energy-Constrained On-Chip Machine Learning (Part 2).
ACM J. Emerg. Technol. Comput. Syst., 2019
Guest Editors' Introduction to the Special Section on Hardware and Algorithms for Energy-Constrained On-chip Machine Learning.
ACM J. Emerg. Technol. Comput. Syst., 2019
IEEE J. Emerg. Sel. Topics Circuits Syst., 2019
High-Throughput In-Memory Computing for Binary Deep Neural Networks with Monolithically Integrated RRAM and 90nm CMOS.
CoRR, 2019
CoRR, 2019
Cases for Analog Mixed Signal Computing Integrated Circuits for Deep Neural Networks.
Proceedings of the International Symposium on VLSI Design, Automation and Test, 2019
FixyNN: Energy-Efficient Real-Time Mobile Computer Vision Hardware Acceleration via Transfer Learning.
Proceedings of the Second Conference on Machine Learning and Systems, SysML 2019, 2019
Proceedings of the International Symposium on Memory Systems, 2019
Proceedings of the 2019 IEEE/ACM International Symposium on Low Power Electronics and Design, 2019
ECG Authentication Neural Network Hardware Design with Collective Optimization of Low Precision and Structured Compression.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019
Neuromorphic Hardware Accelerator for SNN Inference based on STT-RAM Crossbar Arrays.
Proceedings of the 26th IEEE International Conference on Electronics, Circuits and Systems, 2019
Joint Optimization of Quantization and Structured Sparsity for Compressed Deep Neural Networks.
Proceedings of the IEEE International Conference on Acoustics, 2019
Proceedings of the 2019 on Great Lakes Symposium on VLSI, 2019
Proceedings of the 29th International Conference on Field Programmable Logic and Applications, 2019
A 8.93-TOPS/W LSTM Recurrent Neural Network Accelerator Featuring Hierarchical Coarse-Grain Sparsity With All Parameters Stored On-Chip.
Proceedings of the 45th IEEE European Solid State Circuits Conference, 2019
Proceedings of the 45th IEEE European Solid State Circuits Conference, 2019
Proceedings of the 53rd Asilomar Conference on Signals, Systems, and Computers, 2019
2018
A Fixed-Point Neural Network Architecture for Speech Applications on Resource Constrained Hardware.
J. Signal Process. Syst., 2018
IEEE Trans. Very Large Scale Integr. Syst., 2018
IEEE Trans. Circuits Syst. I Regul. Pap., 2018
Power, Performance, and Area Benefit of Monolithic 3D ICs for On-Chip Deep Neural Networks Targeting Speech Recognition.
ACM J. Emerg. Technol. Comput. Syst., 2018
Guest Editors' Introduction: Frontiers of Hardware and Algorithms for On-chip Learning.
ACM J. Emerg. Technol. Comput. Syst., 2018
ALAMO: FPGA acceleration of deep learning algorithms with a modularized RTL compiler.
Integr., 2018
Guest Editorial Low-Power, Adaptive Neuromorphic Systems: Devices, Circuit, Architectures and Algorithms.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2018
IEEE J. Emerg. Sel. Topics Circuits Syst., 2018
CoRR, 2018
A Parallel RRAM Synaptic Array Architecture for Energy-Efficient Recurrent Neural Networks.
Proceedings of the 2018 IEEE International Workshop on Signal Processing Systems, 2018
Algorithm-hardware co-design of single shot detector for fast object detection on FPGAs.
Proceedings of the International Conference on Computer-Aided Design, 2018
Proceedings of the 2018 IEEE International Conference on Acoustics, 2018
Proceedings of the 2018 on Great Lakes Symposium on VLSI, 2018
XNOR-RRAM: A scalable and parallel resistive synaptic architecture for binary neural networks.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018
Fully parallel RRAM synaptic array for implementing binary neural network with (+1, -1) weights and (+1, 0) neurons.
Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018
2017
Triple-Mode, Hybrid-Storage, Energy Harvesting Power Management Unit: Achieving High Efficiency Against Harvesting and Load Power Variabilities.
IEEE J. Solid State Circuits, 2017
Neurocomputing, 2017
Proceedings of the Advances in Computational Intelligence, 2017
Monolithic 3D IC designs for low-power deep neural networks targeting speech recognition.
Proceedings of the 2017 IEEE/ACM International Symposium on Low Power Electronics and Design, 2017
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017
An automatic RTL compiler for high-throughput FPGA implementation of diverse deep convolutional neural networks.
Proceedings of the 27th International Conference on Field Programmable Logic and Applications, 2017
Optimizing Loop Operation and Dataflow in FPGA Acceleration of Deep Convolutional Neural Networks.
Proceedings of the 2017 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2017
Proceedings of the 2017 39th Annual International Conference of the IEEE Engineering in Medicine and Biology Society (EMBC), 2017
Flying and decoupling capacitance optimization for area-constrained on-chip switched-capacitor voltage regulators.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017
Algorithm and hardware design of discrete-time spiking neural networks based on back propagation with binary activations.
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2017
Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017
A real-time 17-scale object detection accelerator with adaptive 2000-stage classification in 65nm CMOS.
Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017
Minimizing area and energy of deep learning hardware design using collective low precision and structured compression.
Proceedings of the 51st Asilomar Conference on Signals, Systems, and Computers, 2017
2016
Reducing Power, Leakage, and Area of Standard-Cell ASICs Using Threshold Logic Flip-Flops.
IEEE Trans. Very Large Scale Integr. Syst., 2016
A Low Ripple Switched-Capacitor Voltage Regulator Using Flying Capacitance Dithering.
IEEE J. Solid State Circuits, 2016
Comprehensive Evaluation of OpenCL-based Convolutional Neural Network Accelerators in Xilinx and Altera FPGAs.
CoRR, 2016
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2016
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016
Proceedings of the IEEE 16th International Conference on Data Mining, 2016
Efficient memory compression in deep neural networks using coarse-grain sparsification for speech applications.
Proceedings of the 35th International Conference on Computer-Aided Design, 2016
Compact oscillation neuron exploiting metal-insulator-transition for neuromorphic computing.
Proceedings of the 35th International Conference on Computer-Aided Design, 2016
Proceedings of the 2016 IEEE International Conference on Acoustics, 2016
Proceedings of the 26th International Conference on Field Programmable Logic and Applications, 2016
Throughput-Optimized OpenCL-based FPGA Accelerator for Large-Scale Convolutional Neural Networks.
Proceedings of the 2016 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2016
Triple-mode photovoltaic power management: Achieving high efficiency against harvesting and load variability.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2016
2015
Parallel Architecture With Resistive Crosspoint Array for Dictionary Learning Acceleration.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2015
A fully-integrated 40-phase flying-capacitance-dithered switched-capacitor voltage regulator with 6mV output ripple.
Proceedings of the Symposium on VLSI Circuits, 2015
Proceedings of the 2015 IFIP/IEEE International Conference on Very Large Scale Integration, 2015
A neuromorphic neural spike clustering processor for deep-brain sensing and stimulation systems.
Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design, 2015
Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design, 2015
Fully-integrated switched-capacitor voltage regulator with on-chip current-sensing and workload optimization in 32nm SOI CMOS.
Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design, 2015
Energy-efficient reconstruction of compressively sensed bioelectrical signals with stochastic computing circuits.
Proceedings of the 33rd IEEE International Conference on Computer Design, 2015
Mitigating Effects of Non-ideal Synaptic Device Characteristics for On-chip Learning.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2015
Technology-design co-optimization of resistive cross-point array for accelerating learning algorithms on chip.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015
Dynamic and leakage power reduction of ASICs using configurable threshold logic gates.
Proceedings of the 2015 IEEE Custom Integrated Circuits Conference, 2015
2014
Neurophysics-inspired parallel architecture with resistive crosspoint array for dictionary learning.
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2014
Proceedings of the 5th Annual International Conference on Biologically Inspired Cognitive Architectures, 2014
2013
A 0.1pJ/b 5-to-10Gb/s charge-recycling stacked low-power I/O for on-chip signaling in 45nm CMOS SOI.
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013
2011
IEEE Trans. Very Large Scale Integr. Syst., 2011
IEEE J. Solid State Circuits, 2011
A 45nm CMOS neuromorphic chip with a scalable architecture for learning in networks of spiking neurons.
Proceedings of the 2011 IEEE Custom Integrated Circuits Conference, 2011
2010
High-bandwidth and low-energy on-chip signaling with adaptive pre-emphasis in 90nm CMOS.
Proceedings of the IEEE International Solid-State Circuits Conference, 2010
In situ delay-slack monitor for high-performance processors using an all-digital self-calibrating 5ps resolution time-to-digital converter.
Proceedings of the IEEE International Solid-State Circuits Conference, 2010
2009
IEEE J. Solid State Circuits, 2009
2008
IEEE Trans. Very Large Scale Integr. Syst., 2008
A robust alternate repeater technique for high performance busses in the multi-core era.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008
Proceedings of the 2008 International Conference on Computer-Aided Design, 2008
Proceedings of the IEEE 2008 Custom Integrated Circuits Conference, 2008
2007
Proceedings of the 8th International Symposium on Quality of Electronic Design (ISQED 2007), 2007