Jae-Soub Han
Orcid: 0000-0003-0287-4011
According to our database1,
Jae-Soub Han
authored at least 7 papers
between 2020 and 2022.
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Bibliography
2022
A 3.2-GHz 178-fs<sub>rms</sub> Jitter Subsampling PLL/DLL-Based Injection-Locked Clock Multiplier.
IEEE Trans. Very Large Scale Integr. Syst., 2022
A 2.5 GS/s 7-Bit 5-Way Time-Interleaved SAR ADC With On-Chip Background Offset and Timing-Skew Calibration.
IEEE Trans. Circuits Syst. II Express Briefs, 2022
A 0.5 V 10 b 3 MS/s 2-Then-1b/Cycle SAR ADC With Digital-Based Time-Domain Reference and Dual-Mode Comparator.
IEEE Trans. Circuits Syst. II Express Briefs, 2022
2021
A Reference-Sampling Based Calibration-Free Fractional-N PLL with a PI-Linked Sampling Clock Generator.
Sensors, 2021
A 3.2 GHz 178fsrms Jitter Injection Locked Clock Multiplier Using Sub-Sampling FTL and DLL for In-Band Noise Improvement.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2021
2020
Time-Interleaved SAR ADC with Background Timing-Skew Calibration for UWB Wireless Communication in IoT Systems.
Sensors, 2020
IEEE Access, 2020